82801CA Datasheet, PDF (331/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.1.1
9.8.1.2
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
A0h
00h
No
Core
Attribute:
Size:
Usage:
R/W
16-bit
ACPI, Legacy
Bit
15:11
10
9
8:6
5
4:2
1:0
Description
Reserved.
Software SMI Rate Select (SWSMI_RATE_SEL)—R/W.
0 = SWSMI Timer will time out in 64 ms ± 4 ms (default).
1 = SWSMI Timer will time out in 1.5 ms ± 0.5 ms.
PWRBTN_LVL—RO. This read-only bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved.
CPU SLP# Enable (CPUSLP_EN)—R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1. This reduces the processor power.
Note that CPUSLP# will go active during Intel^® SpeedStep™ technology transitions and on entry
to S1, S3, S4 and S5 even if this bit is not set.
Reserved.
Periodic SMI# Rate Select (PER_SMI_SEL)—R/W. Set by software to control the rate at which
periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
A2h
00h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI, Legacy
Bit
Description
7:2 Reserved.
CPU Power Failure (CPUPWR_FLR)—R/WC.
1 _{0 = Software clears this bit by writing a 1 to it.}
1 = Indicates that the VRMPWRGD signal, from the processor’s VRM, went low.
PWROK Failure (PWROK_FLR)—R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state.
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. The bit
will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.
NOTE: Traditional designs have a reset button logically AND’d with the PWROK signal from the
0
power supply and the processor’s voltage regulator module. If this is done with the ICH3,
the PWROK_FLR bit will be set. The ICH3 treats this internally as if the RSMRST# signal
had gone active. However, it is not treated as a full power failure. If PWROK goes inactive
and then active (but RSMRST# stays high), then the ICH3 will reboot (regardless of the
state of the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high,
then this is a full power failure, and the reboot policy is controlled by the AFTERG3 bit.
NOTE: VGATE is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period
may not be detected by the ICH3.
Intel^® 82801CA ICH3-S Datasheet
331