82801CA Datasheet, PDF (225/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.5 System Reset
Table 5-101 indicates the states of the link during various system reset and sleep conditions.
Table 5-101. AC-Link State during PCIRST#
Signal
Power Plane
I/O
During
PCIRST#/
After
PCIRST#/
AC_RST#
AC_SDOUT
AC_SYNC
BIT_CLK
SDIN[1:0]
Resume³
Core¹
Core
Core
Resume
Output Low
Low
Output Low
Output Low
Input
Driven by
codec
Input
Driven by
codec
Running
Running
Running
Running
S1
S3
Cold
Reset Low
bit (Hi)
Low Low
Low Low
Low^2,4 Low^2,4
Low^2,4 Low^2,4
S4/S5
Low
Low
Low
Low^2,4
Low^2,4
NOTE:
1. ICH3 core well outputs are used as strapping options for the ICH3, sampled during system reset. These
signals may have weak pullups/pulldowns on them. The ICH3 outputs will be driven to the appropriate level
prior to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core
well to prevent leakage during a suspend state.
2. The pull-down resistors on these signals are only enabled when the AC-link shut off bit in the AC ’97 global
control register is set to 1. All other times, the pull-down resistor is disabled.
3. AC_RST# will be held low during S3–S5. It cannot be programmed high during a suspend state.
4. BIT_CLK and SDIN[1:0] are driven low by the codecs during normal states. If the codec is powered during
suspend states it will hold these signals low. However, if the codec is not present, or not powered in suspend,
external pull-down resistors are required.
The transition of AC_RST# to the deasserted state will only occur under driver control. In the
S1sleep state, the state of the AC_RST# signal is controlled by the AC ’97 Cold Reset# bit (bit 1)
in the global control register. AC_RST# will be asserted (low) by the ICH3 under the following
conditions:
• RSMRST# (system reset, including the a reset of the resume well and PCIRST#)
• Mechanical power up (causes PCIRST#)
• Write to CF9h hard reset (causes PCIRST#)
• Transition to S3/S4/S5 sleep states (causes PCIRST#)
• Write to AC ’97 Cold Reset# bit in the global control register.
Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically.
Only software can deassert the Cold Reset# bit, and hence the AC_RST# signal. This bit, while it
resides in the core well, will remain cleared upon return from S3/S4/S5 sleep states. The AC_RST#
pin will remain actively driven from the resume well, as indicated.
Intel^® 82801CA ICH3-S Datasheet
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