82801CA Datasheet, PDF (339/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.2
PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 02h
(ACPI PM1a_EVT_BLK + 2)
0000h
No
Bits 0:7: Core,
Bits 8, 9: Resume
Bit 10: RTC
Bits 11:15: Resume
Attribute:
Size:
Usage:
R/W
16-bit
ACPI or Legacy
Bit
Description
15:11
10
9
Reserved.
RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event to wake after
a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override
event.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes
active.
Reserved.
Power Button Enable (PWRBTN_EN)—R/W. This bit is used to enable the setting of the
PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no
effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is
8 _{always enabled as a Wake event.}
0 = Disable.
1 = Enable.
7:6 Reserved.
Global Enable (GBL_EN)—R/W. When both the GBL_EN and the GBL_STS are set, an SCI is
raised.
5
0 = Disable.
1 = Enable SCI on GBL_STS going active.
4:1 Reserved.
Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with the SCI_EN bit
as described below:
0 ^TMROF_EN
0
1
1
SCI_EN
x
0
1
Effect when TMROF_STS is set
No SMI# or SCI
SMI#
SCI
Intel^® 82801CA ICH3-S Datasheet
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