82801CA Datasheet, PDF (191/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.16.6.2
Non-Transaction Based Interrupts
If an ICH3 process error or system error occur, the ICH3 halts and immediately issues a hardware
interrupt to the system.
Resume Received
This event indicates that the ICH3 received a RESUME signal from a device on the USB bus
during a global suspend. If this interrupt is enabled in the Interrupt Enable Register, a hardware
interrupt will be signaled to the system allowing the USB to be brought out of the suspend state and
returned to normal operation.
ICH3 Process Error
The HC monitors certain critical fields during operation to ensure that it does not process corrupted
data structures. These include checking for a valid PID and verifying that the MaxLength field is
less than 1280. If it detects a condition that would indicate that it is processing corrupted data
structures, it immediately halts processing, sets the HC process error bit in the HC Status Register
and signals a hardware interrupt to the system.
This interrupt cannot be disabled through the Interrupt Enable Register.
Host System Error
The ICH3 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occur.
When this error occurs, the ICH3 clears the run/stop bit in the USB Command Register to prevent
further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt
Enable Register.
5.16.7 USB Power Management
The Host Controller can be put into a suspended state and its power can be removed. This requires
that certain bits of information are retained in the resume power plane of the ICH3 so that a device
on a port may wake the system. Such a device may be a fax-modem, which will wake up the
machine to receive a fax or take a voice message. The settings of the following bits in I/O space
will be maintained when the ICH3 enters the S3, S4, or S5 states.
Table 5-75. Bits Maintained in Low Power States
Register
Command
Status
Port Status and Control
Offset
00h
02h
10h & 12h
Bit
Description
3 Enter Global Suspend Mode (EGSM)
2 Resume Detect
2 Port Enabled/Disabled
6 Resume Detect
8 Low Speed Device Attached
12 Suspend
When the ICH3 detects a resume event on any of its ports, it will set the corresponding USB_STS
bit in ACPI space. If USB is enabled as a wake/break event, the system will wake up and an SCI
will be generated.
Intel^® 82801CA ICH3-S Datasheet
191