82801CA Datasheet, PDF (21/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

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Intel^® ICH3-S System Configuration ................................................................ 4
Intel^® 82801CA ICH3-S Simplified Block Diagram ........................................38
Required External RTC Circuit.......................................................................53
Example V5REF Sequencing Circuit .............................................................54
Conceptual System Clock Diagram ...............................................................63
Primary Device Status Register Error Reporting Logic..................................67
Secondary Status Register Error Reporting Logic .........................................67
NMI# Generation Logic ..................................................................................68
Integrated LAN Controller Block Diagram......................................................72
64-Word EEPROM Read Instruction Waveform ............................................82
LPC Interface Diagram ..................................................................................85
Typical Timing for LFRAME# .........................................................................89
Abort Mechanism ...........................................................................................90
Intel^® ICH3 DMA Controller ...........................................................................92
DMA Serial Channel Passing Protocol ..........................................................95
DMA Request Assertion Through LDRQ# .....................................................99
Coprocessor Error Timing Diagram .............................................................131
Signal Strapping...........................................................................................134
Physical Region Descriptor Table Entry ......................................................165
Transfer Descriptor ......................................................................................173
Example Queue Conditions .........................................................................181
USB Data Encoding .....................................................................................184
USB Legacy Keyboard Flow Diagram .........................................................192
Intel^® ICH3 Based Audio Codec ’97, Revision 2.2 ......................................213
Audio Codec ’97, Revision 2.2 Controller-Codec Connection .....................214
AC-Link Protocol ..........................................................................................215
AC-Link Powerdown Timing.........................................................................223
SDIN Wake Signaling ..................................................................................224
Intel^® ICH3 Ballout (Topview—Left Side) ....................................................448
Intel^® ICH3 Ballout (Topview—Right Side) ..................................................449
Clock Timing ................................................................................................475
Valid Delay From Rising Clock Edge ...........................................................475
Setup and Hold Times .................................................................................475
Float Delay...................................................................................................475
Pulse Width..................................................................................................476
Output Enable Delay....................................................................................476
IDE PIO Mode..............................................................................................476
IDE Multiword DMA......................................................................................477
Ultra ATA Mode (Drive Initiating a Burst Read) ...........................................477
Ultra ATA Mode (Sustained Burst)...............................................................478
Ultra ATA Mode (Pausing a DMA Burst)......................................................478
Ultra ATA Mode (Terminating a DMA Burst)................................................479
USB Rise and Fall Times.............................................................................479
USB Jitter.....................................................................................................479
USB EOP Width...........................................................................................480
SMBus Transaction......................................................................................480
SMBus Timeout ...........................................................................................480
Power Sequencing and Reset Signal Timings.............................................481
1.8 V/3.3 V Power Sequencing ....................................................................481
Intel^® 82801CA ICH3-S Datasheet
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