82801CA Datasheet, PDF (243/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.1.23
PMCSR—Power Management Control/Status Register
(LAN Controller—B1:D8:F0)
Offset Address: E0–E1h
Default Value: 0000h
Attribute:
Size:
RO, R/W, R/WC
16 bits
Bit
Description
15
14:13
12:9
8
7:5
4
3:2
1:0
PME Status—R/WC.
0 = Software clears this bit by writing a 1 to the bit location. This also de-asserts the PME# signal
and clears the PME status bit in the Power Management Driver Register. When the PME#
signal is enabled, the PME# signal reflects the state of the PME status bit.
1 = Set upon occurrence of a wake-up event, independent of the state of the PME enable bit.
Data Scale—RO. This field indicates the data register scaling factor. It equals 10b for registers zero
through eight and 00b for registers nine through fifteen, as selected by the “Data Select” field.
Data Select—R/W. This field is used to select which data is reported through the Data register and
Data Scale field.
PME Enable—R/W. This bit enables the ICH3’s integrated LAN controller to assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
Reserved.
Dynamic Data—RO. Hardwired to 0 to indicate that the device does not support the ability to
monitor the power consumption dynamically.
Reserved.
Power State—R/W. This 2-bit field is used to determine the current power state of the integrated
LAN Controller, and to put it into a new power state. The definition of the field values is as follows:
00 = D0
01 = D1
10 = D2
11 = D3
Intel^® 82801CA ICH3-S Datasheet
243