82801CA Datasheet, PDF (443/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Modem Controller Registers (D31:F6)
14.2.8
GLOB_CNT—Global Control Register
I/O Address:
Default Value:
Lockable:
MBAR + 3Ch
00000000h
No
Attribute:
Size:
Power Well:
R/W
32 bits
Core
Bit
Description
Reserved.
31:6 NOTE: Software must preserve the value of these bits when writing to this register. This can be
achieved by either not writing to the upper two bytes at all (with byte-writes to this register
enabled) or by performing a read-modify-write to the entire 4-byte register.
Secondary Resume Interrupt Enable—R/W.
5
0 = Disable.
1 = Enable an interrupt to occur when the secondary codec causes a resume event on the AC-
link.
Primary Resume Interrupt Enable—R/W.
4
0 = Disable.
1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link.
ACLINK Shut Off—R/W.
3
0 = Normal operation.
1 = Disable the AC-link signals (drive all AC ’97 outputs low and turn off all AC ’97 input buffer
enables).
AC ’97 Warm Reset—R/W (special).
0 = This bit is self-clearing (it clears itself after the reset has occurred and BIT_CLK has started).
2
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken
a suspended codec without clearing its internal registers. If software attempts to perform a
warm reset while BIT_CLK is running, the write will be ignored and the bit will not be changed.
A warm reset can only occur in the absence of BIT_CLK.
AC ’97 Cold Reset#—R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ’97 circuitry. All data in
1
the codec will be lost. Software needs to clear this bit no sooner than the minimum number of
ms have elapsed.
1 = This bit defaults to 0; hence, after reset, the driver needs to set this bit to a 1.
GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI
causes an interrupt.
0
0 = Bit 0 of the Global Status Register is set, but an interrupt is not generated.
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
Intel^® 82801CA ICH3-S Datasheet
443