82801CA Datasheet, PDF (123/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.8.5.5 Interrupt Message Format
The ICH3 writes the message to PCI (and to the Host Controller) as a 32-bit memory write cycle. It
uses the formats shown in Table 5-25 and Table 5-26 for the Address and Data.
The local APIC (in the processor) has a delivery mode option to interpret Processor System Bus
messages as an SMI in which case the processor treats the incoming interrupt as an SMI instead of
as an interrupt. This does not mean that the ICH3 has any way to have an SMI source from ICH3
power management logic cause the IOAPIC to send an SMI message (there is no way to do this).
The ICH3’s IOAPIC can only send interrupts due to interrupts which do not include SMI, NMI or
INIT. This means that in IA32/IA64 based platforms, Processor System Bus interrupt message
format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section,
must not be used and is not supported. Only the hardware pin connection is supported by the ICH3.
:
Table 5-25. Interrupt Message Address Format
Bit
31:20
19:12
11:4
3
2
1:0
Description
Will always be FEEh
Destination ID: This will be the same as bits 63:56 of the I/O Redirection Table entry for the
interrupt associated with this message.
RESERVED (will always be 0)
Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be
redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:12.
1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from
bits 10:8 in the Data Field (see below).
The redirection hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding
interrupt are encoded as 001 (Lowest Priority). Otherwise, the redirection hint bit will be 0
Destination Mode: This bit is used only the redirection hint bit is set to 1. If the redirection hint bit
and the destination mode bit are both set to 1, then the logical destination mode is used, and the
redirection is limited only to those processors that are part of the logical group as based on the
logical ID.
Will always be 00.
Table 5-26. Interrupt Message Data Format
Bit
31:16
15
14
13:12
11
10:8
7:0
Description
Will always be 0000h.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for
that interrupt.
Delivery Status: 1 = Assert, 0 = Deassert.
If using edge-triggered interrupts, then bit will always be 1, since only the assertion is sent.
If using level-triggered interrupts, then this bit indicates the state of the interrupt input.
Will always be 00
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O Redirection
Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
Intel^® 82801CA ICH3-S Datasheet
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