82801CA Datasheet, PDF (159/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.14 General Purpose I/O
5.14.1 GPIO Mapping
Table 5-51. GPIO(s) Mapping
Name/
Muxed
Function
Usage
Muxed I/O
Pwr
Plan
Tolerant
Wake
Event
Support
Wake
from
State
After
RSMRST#
After
PCIRST#
GPI[0] /
REQ[A]#
REQ[A] for PC/PCI header Yes
GPI[1] /
REQ[B]#/
REQ[5]#
REQ[5]# for 6th PCI device Yes
GPI[2] /
PIRQE#
PIRQ[E] will be routed
internally when this pin is
Yes
used as GPIO[x]
GPI[3] /
PIRQF#
PIRQ[F] will be routed
internally when this pin is
Yes
used as GPIO[x]
GPI[4] /
PIRQG#
PIRQ[G] will be routed
internally when this pin is
used as GPIO[x]
Yes
GPI[5] /
PIRQH#
PIRQ[H] will be routed
internally when this pin is
Yes
used as GPIO[x]
GPI[7]
If this pin is unused, then it
should not matter which
level is considered active.
No
An external pull up or down
resister is required.
GPI[8]
If this pin is unused, then it
should not matter which
level is considered active.
No
An external pull up/down
resister is required.
In heartbeat mode (G1 or
hung-G0), this pin will
GPI[11] /
SMBALERT#
trigger an event (detected
via a transition) and send
out the alert message,
Yes
regardless it is programmed
as GPIO or not.
GPI[12]
No
GPI[13]
GPO[16] /
GNT[A]#
GPO[17] /
GNT[B]# /
GNT[5]#
No
GNT[A] for
PC/PCI header
Yes
GNT[5]# for 6th PCI device Yes
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Core
5.0 V
Wake /
SMI# / SCI
S1
I
Resume
3.3 V
Wake /
SMI# / SCI
S1–S5
High
I
Resume
3.3 V
Wake /
SMI# / SCI
S1–S5
High
I Resume
I Resume
O Core
3.3 V
3.3 V
5.0 V
Wake /
SMI# / SCI
S1–S5
Wake /
SMI# / SCI
S1–S5
—
—
Defined
Defined
High²
O Core
5.0 V
—
—
High²
[2]
[2]
[2]
[2]
[2]
[2]
—
—
—
—
—
High²
High²
Intel^® 82801CA ICH3-S Datasheet
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