82801CA Datasheet, PDF (289/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.24
9.1.25
RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)
Offset Address: D8h
Default Value: 00h
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:5 Reserved.
Upper 128-byte Lock (U128LOCK)—R/W (special).
0 = Access to these bytes in the upper CMOS RAM range have not been locked.
4 _{1 = Locks reads and writes to bytes 38h–3Fh in the upper 128-byte bank of the RTC CMOS RAM.}
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
Lower 128-byte Lock (L128LOCK)—R/W (special).
0 = Access to these bytes in the lower CMOS RAM range have not been locked.
3 _{1 = Locks reads and writes to bytes 38h–3Fh in the lower 128-byte bank of the RTC CMOS RAM.}
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
Upper 128-byte Enable (U128E)—R/W.
2 _{0 = Disable.}
1 = Enables access to the upper 128-byte bank of RTC CMOS RAM.
1:0 Reserved.
COM_DEC—LPC I/F Communication Port Decode Ranges
Register (LPC I/F—D31:F0)
Offset Address: E0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7 Reserved.
COMB Decode Range—R/W. This field determines which range to decode for the COMB Port.
Bits
000
001
6:4 ⁰¹⁰
011
100
101
110
111
Decode Range
3F8h–3FFh (COM1)
2F8h–2FFh (COM2)
220h–227h
228h–22Fh
238h–23Fh
2E8h–2EFh (COM4)
338h–33Fh
3E8h–3EFh (COM3)
3 Reserved.
COMA Decode Range—R/W. This field determines which range to decode for the COMA Port.
Bits
000
001
2:0 ⁰¹⁰
011
100
101
110
111
Decode Range
3F8h–3FFh (COM1)
2F8h–2FFh (COM2)
220h–227h
228h–22Fh
238h–23Fh
2E8h–2EFh (COM4)
338h–33Fh
3E8h–3EFh (COM3)
Intel^® 82801CA ICH3-S Datasheet
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