82801CA Datasheet, PDF (166/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
The bus master IDE active bit in Bus Master IDE Status Register is reset automatically when the
controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in
last PRD). The IDE interrupt status bit is set when the IDE device generates an interrupt. These
events may occur prior to line buffer emptying for memory writes. If either of these conditions
exist, all PCI Master non-Memory read accesses to ICH3 are retried until all data in the line buffers
has been transferred to memory.
5.15.2.2
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The
DMA Timing Enable Only bits in the IDE Timing Register can be used to program fast timing
mode for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are
faster that its PIO transfer timings. The IDE device DMA request signal is sampled on the same
PCI clock that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is
deasserted on the next PCI clock and no more transfers take place until DMA request is asserted
again.
5.15.2.3 Interrupts
Legacy Mode
The ICH3 is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.
This connection is done from the ISA pin, before any mask registers. This implies the following:
• Bus Master IDE devices are connected directly off of ICH3. IDE interrupts cannot be
communicated through PCI devices or the serial stream.
Warning: In this mode, the ICH3 will not drive the PCI Interrupt associated with this function. That is only
used in native mode.
Native Mode
In this case both the Primary and Secondary channels share an interrupt. It will be internally
connected to PIRQ[C]# (IRQ18 in APIC mode).
The interrupt will be active-low and shared.
Behavioral notes in native mode:
• The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the interrupt
controllers. The IDE logic forces these signals inactive in such a way that the Serial IRQ
source may be used.
• The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt controller can
come from other sources (Serial IRQ, PIRQx).
• The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
• When switching the IDE controller to native mode, the IDE Interrupt Pin Register (see Section
11.1.16) will be masked. If an interrupt occurs while the masking is in place and the interrupt
is still active when the masking ends, the interrupt will be allowed to be asserted.*
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Intel^® 82801CA ICH3-S Datasheet