82801CA Datasheet, PDF (357/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.9.10
9.9.11
9.9.12
TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address:
Default Value:
Lockable:
TCOBASE +0Ch (Message 1) Attribute:
TCOBASE +0Dh (Message 2)
00h
Size:
No
Power Well:
R/W
8-bit
Resume
Bit
Description
TCO_MESSAGE[n]—R/W.The value written into this register will be sent out via the SMLINK
7:0 interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this register to
indicate its boot progress which can be monitored externally.
TCO_WDSTATUS—TCO2 Control Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 0Eh
00h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
Watchdog Status (WDSTATUS)—R/W. The value written to this register will be sent in the Alert On
7:0
LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 10h
03h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved.
IRQ12_CAUSE—R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by
1 the ICH3’s SERIRQ logic. This bit must be a “1” (default) if the ICH3 is expected to receive IRQ12
assertions from a SERIRQ device.
IRQ1_CAUSE—R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
0 the ICH3’s SERIRQ logic. This bit must be a “1” (default) if the ICH3 is expected to receive IRQ1
assertions from a SERIRQ device.
Intel^® 82801CA ICH3-S Datasheet
357