82801CA Datasheet, PDF (362/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.10.5
GPO_BLINK—GPO Blink Enable Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +18h
0004 0000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
Description
31:29, 26,
24:20, 17:0
Reserved.
28:27, 25
GP_BLINK[n]—R/W. The setting of these bits will have no effect if the corresponding GPIO is
programmed as an input. These bits correspond to GPIO that are in the Resume well, and will
be reset to their default values by RSMRST# but not by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate
of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
19:18
GP_BLINK[n]—R/W. The setting of these bits will have no effect if the corresponding GPIO is
programmed as an input. These bits correspond to GPIO that are in the Core well, and will be
reset to their default values by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate
of approximately once per second. The high and low times are approximately 0.5 seconds
each. The GP_LVL bit is not altered when this bit is set.
Note: GPIO[18] blinks by default immediately after reset. This signal could be connected to an LED to
indicate a failed boot (by programming BIOS to clear GP_BLINK[18] after successful POST).
9.10.6
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +2Ch
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
31:14, 10:9
13:11, 8
7:0
Description
Reserved.
GP_INV[n]—R/W. These bits are used to allow both active-low and active-high inputs to
cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least
2 PCI clocks to ensure detection by the ICH3. In the S3, S4 or S5 states the input signal must
be active for at least 2 RTC clocks to ensure detection. The setting of these bits will have no
effect if the corresponding GPIO is programmed as an output. These bits correspond to GPIO
that are in the Resume well, and will be reset to their default values by RSMRST# but not by
PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH3 detects the state of the input
pin to be high.
1 = The corresponding GPI_STS bit will be set when the ICH3 detects the state of the input
pin to be low.
GP_INV[n]—R/W. These bits are used to allow both active-low and active-high inputs to
cause SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least
2 PCI clocks to ensure detection by the ICH3. The setting of these bits will have no effect if
the corresponding GPIO is programmed as an output. These bits correspond to GPIO that
are in the Core well, and will be reset to their default values by PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH3 detects the state of the input
pin to be high.
1 = The corresponding GPI_STS bit will be set when the ICH3 detects the state of the input
pin to be low.
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Intel^® 82801CA ICH3-S Datasheet