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82801CA Datasheet, PDF (291/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S) | |||
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LPC I/F Bridge Registers (D31:F0)
9.1.28
FWH_DEC_EN1âFWH Decode Enable 1 Register
(LPC I/FâD31:F0)
Offset Address: E3h
Default Value: FFh
Attribute:
Size:
R/W
8 bits
This register determines which memory ranges will be decoded on the PCI bus and forwarded to
the FWH. The ICH3 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
Bit
Description
FWH_F8_ENâRO. Enables decoding two 512 KB FWH memory ranges, and one 128 KB memory
range.
7
1 = Enable the following ranges for the FWH
FFF80000hâFFFFFFFFh
FFB80000hâFFBFFFFFh
000E0000hâ000FFFFFh
FWH_F0_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
6 1 = Enable the following ranges for the FWH:
FFF00000hâFFF7FFFFh
FFB00000hâFFB7FFFFh
FWH_E8_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
5 1 = Enable the following ranges for the FWH:
FFE80000hâFFEFFFFh
FFA80000hâFFAFFFFFh
FWH_E0_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
4 1 = Enable the following ranges for the FWH:
FFE00000hâFFE7FFFFh
FFA00000hâFFA7FFFFh
FWH_D8_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
3 1 = Enable the following ranges for the FWH
FFD80000hâFFDFFFFFh
FF980000hâFF9FFFFFh
FWH_D0_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
2 1 = Enable the following ranges for the FWH
FFD00000hâFFD7FFFFh
FF900000hâFF97FFFFh
FWH_C8_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
1 1 = Enable the following ranges for the FWH
FFC80000hâFFCFFFFFh
FF880000hâFF8FFFFFh
FWH_C0_ENâR/W. Enables decoding two 512 KB FWH memory ranges.
0 = Disable.
0 1 = Enable the following ranges for the FWH
FFC00000hâFFC7FFFFh
FF800000hâFF87FFFFh
Intel® 82801CA ICH3-S Datasheet
291
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