82801CA Datasheet, PDF (42/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
Table 2-5. PCI Interface Signals (Continued)
Name
PLOCK#
SERR#
PME#
REQ[A]# /
GPIO[0]
REQ[B]# /
REQ[5]# /
GPIO[1]
GNT[A]# /
GPIO[16]
GNT[B]# /
GNT[5]# /
GPIO[17]
Type
Description
I/O
I/OD
I/OD
I
O
PCI Lock: Indicates an exclusive bus operation and may require multiple
transactions to complete. ICH3 asserts PLOCK# when it performs non-exclusive
transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted
the bus.
System Error: SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the ICH3 has the ability to
generate an NMI, SMI#, or interrupt.
PCI Power Management Event: PCI peripherals drive PME# to wake the system
from low-power states S1–S5. PME# assertion can also be enabled to generate
an SCI from the S0 state. In some cases the ICH3 may drive PME# active due to
an internal wake event. The ICH3 will not drive PME# high, but it will be pulled up
to VccSus3_3 by an internal pull-up resistor.
PC/PCI DMA Request [B:A]: This request serializes ISA-like DMA Requests for
the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used
by devices such as PCI based Super I/O or audio codecs which need to perform
legacy Intel^® 8237 DMA but have no ISA bus.
When not used for PC/PCI requests, these signals can be used as General
Purpose Inputs. REQ[B]# can instead be used as the sixth PCI bus request.
PC/PCI DMA Acknowledges [B: A]: This grant serializes an ISA-like DACK# for
the purpose of running DMA/ISA Master cycles over the PCI bus. This is used by
devices such as PCI based Super/IO or audio codecs which need to perform
legacy Intel 8237 DMA but have no ISA bus.
When not used for PC/PCI, these signals can be used as General Purpose
Outputs. GNTB# can also be used as the sixth PCI bus master grant output.
These signal have internal pull-up resistors.
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Intel^® 82801CA ICH3-S Datasheet