82801CA Datasheet, PDF (520/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Bit Index
Read/Write Selection Status................................307
Real Time Clock Index Address (RTC_INDX) .. 328
Receive DMA Byte Count .................................. 251
Receive Not Ready (RNR) .................................. 246
Receive Unit Command (RUC) .......................... 248
Receive Unit Status (RUS).................................. 246
Received Master Abort (RMA).. 262, 266, 367, 383,
400
Received System Error (SSE) ..................... 262, 266
Received Target Abort (RTA).... 237, 262, 266, 278,
400
Recovery Time (RCT)......................................... 372
Redirection Entry Clear.......................................318
Refresh Cycle Toggle (REF_TOGGLE)............. 327
Register Read Command..................................... 313
Register Result .................................................... 250
Remote IRR......................................................... 320
REQ5#/GNT5# PC/PCI Protocol Select
(PCPCIB_SEL) ................................... 286
Reset CPU (RST_CPU).......................................329
Reset Registers (RR) ...................................426, 442
Resource Indicator....................................... 280, 282
Resource Type Indicator (RTE) . 369, 370, 385, 417,
435
Resume Detect (RSM_DET)....................... 393, 396
Resume Interrupt Enable ..................................... 394
Revision Identification Value..... 237, 263, 278, 367,
401, 415, 433
RI_EN.................................................................. 344
RI_STS ................................................................ 343
RNR Mask........................................................... 247
ROM Content Result ...........................................250
Rotate and EOI Codes (R, SL, EOI) ................... 312
RTC Event Enable (RTC_EN) ............................ 339
RTC Power Status (RTC_PWR_STS) ................ 332
RTC Status (RTC_STS) ...................................... 337
Run/Pause Bus Master (RPBM).................. 426, 442
Run/Stop (RS) ..................................................... 391
S
SAFE_MODE ..................................................... 288
SB16 Decode Range............................................ 290
SB16_LPC_EN ................................................... 293
SCB General Pointer ...........................................249
SCI Enable (SCI_EN) ......................................... 340
SCI IRQ Select (SCI_IRQ_SEL) ........................ 280
Secondary Bus Number.......................................264
Secondary Bus Reset ...........................................269
Secondary Codec ID (SCID)............................... 419
Secondary Codec Ready (SCR) .................. 428, 444
Secondary Drive 0 Base Clock (SCBO)..............376
Secondary Drive 0 Cycle Time (SCT0) ..............375
Secondary Drive 0 Synchronous DMA Mode
Enable (SSDE0) .................................. 374
Secondary Drive 1 Base Clock (SCB1) ..............376
Secondary Drive 1 Cycle Time (SCT1) ..............375
Secondary Drive 1 IORDY Sample Point
(SISP1) ................................................ 373
Secondary Drive 1 Recovery Time (SRCT1)...... 373
Secondary Drive 1 Synchronous DMA
Mode Enable (SSDE1) ........................374
Secondary Master Channel Cable Reporting ......376
Secondary Resume Interrupt Enable ...........427, 443
Secondary Resume Interrupt (SRI) .............428, 444
Secondary Slave Channel Cable Reporting.........376
SECOND_TO_STS ............................................. 355
SEC_SIG_MODE................................................ 376
SEND_NOW .......................................................356
Serial Bus Release Number .................................386
Serial IRQ Enable (SIRQEN)..............................283
Serial IRQ Frame Size (SIRQSZ) .......................283
Serial IRQ Mode Select (SIRQMD)....................283
SERIRQ_SMI_STS ............................................. 347
SERR# Due to Delayed Transaction
Timeout (SERR_DTT) ................273, 285
SERR# Due to Received Target Abort
(SERR_RTA) ..............................273, 285
SERR# Enable .....................................................269
SERR# Enable on Delayed Transaction
Timeout (SERR_DTT_EN).................272
SERR# Enable on Receiving Target Abort
(SERR_RTA_EN) ...............................272
SERR# Enable (SERR_EN)236, 261, 277, 366, 382,
400, 414, 432
SERR# NMI Source Status
(SERR#_NMI_STS) ............................ 327
SERR# on Delayed Transaction Timeout
Enable (SERR_DTT_EN) ...................284
SERR# on Received Target Abort Enable
(SERR_RTA_EN) ...............................284
Short Packet Interrupt Enable..............................394
Signaled System Error (SSE) .....237, 278, 367, 400,
415, 433
Signaled Target Abort (STA) .....237, 262, 266, 278,
367, 383, 400, 415, 433
Single or Cascade (SNGL) ..................................309
Slave Identification Code ....................................311
SLAVE_ADDR ................................................... 408
Sleep Enable (SLP_EN) ......................................340
Sleep Type (SLP_TYP).......................................340
SLP_SMI_EN ...................................................... 346
SLP_SMI_STS ....................................................348
SMBALERT_DIS ...............................................410
SMBALERT_STS ............................................... 405
SMBCLK_CTL ...................................................409
SMBCLK_CUR_STS .........................................409
SMBDATA_CUR_STS ......................................409
SMBus Host Enable (HST_EN)..........................403
SMBus SMI Status (SMBUS_SMI_STS) ...........347
SMBus Wake Status (SMB_WAK_STS) ...........343
SMB_CMD .........................................................406
SMB_FOR_BIOS ................................................ 297
SMB_SMI_EN ....................................................403
SMI at End of Pass-through Enable
(SMIATENDPS) .................................387
SMI Caused by End of Pass-through
(SMIBYENDPS) .................................386
SMI Caused by Port 60 Read (TRAPBY60R) ....387
SMI Caused by Port 60 Write (TRAPBY60W) ..387
SMI Caused by Port 64 Read (TRAPBY64R) ....387
SMI Caused by Port 64 Write (TRAPBY64W) ..387
Intel^® 82801CA ICH3-S Datasheet
520