82801CA Datasheet, PDF (495/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Register Index
A
Table A-1. Intel^® ICH3 PCI Configuration Registers
Register Name
Offset
Datasheet Section and Location
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Master Latency Timer
Header Type
CSR Memory-Mapped Base
Address
CSR I/O-Mapped Base Address
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line Register
Interrupt Pin Register
Minimum Grant Register
Maximum Latency Register
LAN Controller (B1:D8:F0)
00–01h
Section 7.1.1, “VID—Vendor ID Register (LAN
Controller—B1:D8:F0)” on page 7-236
02–03h
04–05h
Section 7.1.2, “DID—Device ID Register (LAN
Controller—B1:D8:F0)” on page 7-236
Section 7.1.3, “PCICMD—PCI Command Register (LAN
Controller—B1:D8:F0)” on page 7-236
06–07h
08h
Section 7.1.4, “PCISTS—PCI Status Register (LAN
Controller—B1:D8:F0)” on page 7-237
Section 7.1.5, “REVID—Revision ID Register (LAN
Controller—B1:D8:F0)” on page 7-237
09h
0Ah
Section 7.1.6, “SCC—Sub Class Code Register (LAN
Controller—B1:D8:F0)” on page 7-238
0Bh
Section 7.1.7, “BCC—Base Class Code Register (LAN
Controller—B1:D8:F0)” on page 7-238
0Ch
Section 7.1.8, “CLS—Cache Line Size Register (LAN
Controller—B1:D8:F0)” on page 7-238
0Dh
Section 7.1.9, “PMLT—PCI Master Latency Timer
Register (LAN Controller—B1:D8:F0)” on page 7-238
0Eh
Section 7.1.10, “HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)” on page 7-239
10–13h
14–17h
Section 7.1.11, “CSR_MEM_BASE CSR—Memory-
Mapped Base Address Register (LAN Controller—
B1:D8:F0)” on page 7-239
Section 7.1.12, “CSR_IO_BASE—CSR I/O-Mapped
Base Address Register (LAN Controller—B1:D8:F0)” on
page 7-239
2C–2Dh
2E–2Fh
Section 7.1.13, “SVID—Subsystem Vendor ID Register
(LAN Controller—B1:D8:F0)” on page 7-240
Section 7.1.14, “SID—Subsystem ID Register (LAN
Controller—B1:D8:F0)” on page 7-240
34h
Section 7.1.15, “CAP_PTR—Capabilities Pointer
Register (LAN Controller—B1:D8:F0)” on page 7-240
3Ch
Section 7.1.16, “INT_LN—Interrupt Line Register (LAN
Controller—B1:D8:F0)” on page 7-241
3Dh
Section 7.1.17, “INT_PN—Interrupt Pin Register (LAN
Controller—B1:D8:F0)” on page 7-241
3Eh
Section 7.1.18, “MIN_GNT—Minimum Grant Register
(LAN Controller—B1:D8:F0)” on page 7-241
3Fh
Section 7.1.19, “MAX_LAT—Maximum Latency Register
(LAN Controller—B1:D8:F0)” on page 7-241
Intel^® 82801CA ICH3-S Datasheet
495