82801CA Datasheet, PDF (336/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3 Power Management I/O Registers
Table 9-10 shows the registers associated with ACPI and Legacy power management support.
These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be
moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the
ACPI 1.0 specification, and use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
Table 9-10. ACPI and Legacy I/O Register Map
PMBASE+
Offset
Register Name
00–01h
02–03h
PM1 Status
PM1 Enable
04–07h PM1 Control
08–0Bh PM1 Timer
0C–0Fh Reserved
10h–13h Processor Control
14h
15–27h
28–29h
2A–2Bh
Level 2 Register
Reserved
General Purpose Event 0 Status
General Purpose Event 0 Enables
2C–2D General Purpose Event 1 Status
2E–2F General Purpose Event 1 Enables
30–31h SMI# Control and Enable
34–35h SMI Status Register
36–3Fh Reserved
40–41h
41–43h
44–45h
Monitor SMI Status
Reserved
Device Trap Status
48–49h Trap Enable register
4Ch–4Dh Bus Address Tracker
4Eh
Bus Cycle Tracker
4Fh–5Fh Reserved
60h–7Fh Reserved for TCO Registers
ACPI Pointer
PM1a_EVT_BLK
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PMTMR_BLK
—
P_BLK
P_BLK+4
—
GPE0_BLK
GPE0_BLK+2
GPE1_BLK
GPE1_BLK+2
—
—
—
—
—
—
—
—
—
—
—
Default
0000h
0000h
00000000h
00000000h
—
00000000h
00h
—
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
—
0000h
0000h
Last Cycle
Last Cycle
—
—
Attributes
R/W
R/W
R/W
RO
—
R/W
RO
—
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
—
R/W
R/W
RO
RO
—
—
336
Intel^® 82801CA ICH3-S Datasheet