82801CA Datasheet, PDF (472/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Electrical Characteristics
Table 16-13. IOAPIC Bus Timing
Sym
t120
t121
t122
Parameter
APICCD[1:0]# Valid Delay from APICCLK Rising
APICCD[1:0]# Setup Time to APICCLK Rising
APICCD[1:0]# Hold Time from APICCLK Rising
Min Max Units Notes Fig
3.0 12.0
ns
8.5
ns
3.0
ns
16-2
16-3
16-3
NOTE: The Min AC column indicates the minimum times required by the SMBus and/or I²C specifications. The
ICH3 tolerates these timings on both its SMBus and SMLink interfaces.
Table 16-14. SMBus Timing
Sym
Parameter
Min Max
t130 Bus Tree Time Between Stop and Start Condition
4.7
t131
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
4.0
t132 Repeated Start Condition Setup Time
4.7
t133 Stop Condition Setup Time
4.0
t134 Data Hold Time
0
t135 Data Setup Time
250
t136 Device Time Out
25
35
t137 Cumulative Clock Low Extend Time (slave device)
25
t138 Cumulative Clock Low Extend Time (master device)
10
Units
µs
µs
µs
µs
ns
ns
ms
ms
ms
Notes Fig
16-16
16-16
16-16
16-16
4 16-16
16-16
1
2 16-17
3 16-17
NOTES:
1. A device will timeout when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
4. t134 has a minimum timing for I²C of 0 ns, while the minimum timing for SMBus is 300 ns.
Table 16-15. AC ’97 Timing
Sym
Parameter
t140 ACSDIN[0:1] Setup to Falling Edge of BITCLK
t141 ACSDIN[0:1] Hold from Falling Edge of BITCLK
t142
ACSYNC, ACSDOUTvalid delay from rising edge of
BITCLK
Min Max
15
5
15
Units
ns
ns
ns
Notes Fig
16-2
Table 16-16. LPC Timing
Sym
Parameter
t150 LAD[3:0] Valid Delay from PCICLK Rising
t151 LAD[3:0] Output Enable Delay from PCICLK Rising
t152 LAD[3:0] Float Delay from PCICLK Rising
t153 LAD[3:0] Setup Time to PCICLK Rising
t154 LAD[3:0] Hold Time from PCICLK Rising
t155 LDRQ[1:0]# Setup Time to PCICLK Rising
t156 LDRQ[1:0]# Hold Time from PCICLK Rising
t157 LFRAME# Valid Delay from PCICLK Rising
Min Max
2
11
2
28
7
0
12
0
2
12
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Fig
16-2
16-6
16-4
16-3
16-3
16-3
16-3
16-2
472
Intel^® 82801CA ICH3-S Datasheet