82801CA Datasheet, PDF (117/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Short Message
Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT and Lowest Priority
with Focus processor interrupts. The delivery mode bits (M2–M0) specify the message. All short
messages take 21 cycles including the idle cycle.
Table 5-21. Short Message
Cycle
1
2–5
Bit 1
1
ARBID
6
NOT(DM)
7
NOT(M1)
8
NOT(L)
9
NOT(V7)
10
NOT(V5)
11
NOT(V3)
12
NOT(V1)
13
NOT(D7)
14
NOT(D5)
15
NOT(D3)
16
NOT(D1)
17
NOT(C1)
18
1
19
NOT(A)
20
NOT(A1)
21
1
Bit 0
0
1
NOT(M2)
NOT(M0)
NOT(TM)
NOT(V6)
NOT(V4)
NOT(V2)
NOT(V0)
NOT(D6)
NOT(D4)
NOT(D2)
NOT(D0)
NOT(C0)
1
NOT(A)
NOT(A1)
1
Comments
Normal Arbitration
Arbitration ID
DM¹ = Destination Mode from bit 11 of the redirection table
register
M2-M0 = Delivery Mode from bits 10:8 of the redirection table
register
L = Level, TM = Trigger Mode
Interrupt vector bits V7–V0 from redirection table register
Destination field from bits 63:56 of redirection table register¹
Checksum for Cycles 6–16²
Postamble³
Status Cycle 0. See Table 5-22.
Status Cycle 1. See Table 5-22.
Idle
NOTES:
1. If DM is 0 (physical mode), then cycles 15 and 16 are the APIC ID and cycles 13 and 14 are sent as 1. If DM
is 1 (logical mode), then cycles 13 through 16 are the 8-bit Destination field. The interpretation of the logical
mode 8-bit Destination field is performed by the local units using the destination format register. Shorthands
of “all-incl-self” and “all-excl-self” both use physical destination mode and a destination field containing APIC
ID value of all ones. The sending APIC knows whether it should (incl) or should not (excl) respond to its own
message.
2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-7). The APIC
driving the message provides this checksum. This, in essence, is the lower two bits of an adder at the end of
the message.
3. This cycle allows all APICs to perform various internal computations based on the information contained in
the received message. One of the computations takes the checksum of the data received in cycles 6 through
16 and compares it with the value in cycle 18. If any APIC computes a different checksum than the one
passed in cycle 17, then that APIC will signal an error on the APIC bus (“00”) in cycle 19. If this happens, all
APICs assume the message was never sent and the sender must try sending the message again, which
includes re-arbitrating for the APIC bus. In lowest priority delivery when the interrupt has a focus processor,
the focus processor signals this by driving a “01” during cycle 19. This indicates to all the other APICs that the
interrupt has been accepted, the arbitration is preempted, and short message format is used. Cycle 19 and
20 indicates the status of the message (i.e., accepted, check sum error, retry or error). Table 5-22 shows the
status signal combinations and their meanings for all delivery modes.
Intel^® 82801CA ICH3-S Datasheet
117