82801CA Datasheet, PDF (359/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Table 9-12. Summary of GPIO Implementation (Continued)
GPIO
Type
Alternate
Function
(Note 1)
GPIO[24]
Input /
Output
Unmuxed
GPIO[25]
Input /
Output
Unmuxed
GPIO[26] N/A N/A
GPIO[27:28]
Input /
Output
Unmuxed
GPIO[29:31] N/A N/A
GPIO[32:43] I/O
Unmuxed
GPIO[44:48] I/O
Unmuxed
Power
Well
Notes
Input active status read from GP_LVL register bit 24.
Resume Output controlled via GP_LVL register bit 24.
TTL driver output
Resume
Blink enabled via GPO_BLINK register bit 25.
Input active status read from GP_LVL register bit 25
Output controlled via GP_LVL register bit 25.
TTL driver output
N/A Not implemented
Input active status read from GP_LVL register bits [27:28]
Resume Output controlled via GP_LVL register bits [27:28]
TTL driver output
N/A Not implemented
Core
Input active status read from GP_LVL2 register bits
[32:43]. Output controlled via GP_LVL2 register bits
[32:43]
Not implemented
NOTES:
1. All GPIOs default to their alternate function.
2. All inputs are sticky. The status bit will remain set as long as the input was asserted for 2 clocks. GPIs are
sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.
3. GPIO[0:7] are 5V tolerant, and all GPIs can be routed to cause an SCI or SMI#
4. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See
Section 9.1.22.
Intel^® 82801CA ICH3-S Datasheet
359