82801CA Datasheet, PDF (190/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Interrupt on Completion
Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The
completion of the transaction associated with that block causes the USB interrupt bit in the HC
Status Register to be set at the end of the frame in which the transfer completed. When a TD is
encountered with the IOC bit set to 1, the IOC bit in the HC status register is set to 1 at the end of
the frame if the active bit in the TD is set to 0 (even if it was set to zero when initially read).
If the IOC enable bit of Interrupt Enable Register (bit 2 of I/O offset 04h) is set, a hardware
interrupt is signaled to the system. The USB interrupt bit in the HC status register is set either when
the TD completes successfully or because of errors. If the completion is because of errors, the USB
error bit in the HC status register is also set.
Short Packet Detect
A transfer set is a collection of data which requires more than 1 USB transaction to completely
move the data across the USB. An example might be a large print file which requires numerous
TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than
the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion
of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in
a TD indicates to the HC to set the USB interrupt bit in the HC Status Register at the end of the
frame in which this event occurs. This feature streamlines the processing of input on these transfer
types. If the short packet interrupt enable bit in the Interrupt Enable Register is set, a hardware
interrupt is signaled to the system at the end of the frame where the event occurred.
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it is said to
be babbling. Since isochrony can be destroyed by a babbling device, this error results in the active
bit in the TD being cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field
is not decremented for a babble. The USB error interrupt bit in the HC status register is set to 1 at
the end of the frame. A hardware interrupt is signaled to the system.
If an EOF babble was caused by the ICH3 (due to incorrect schedule for instance), the ICH3 will
force a bit stuff error followed by an EOP and the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a transaction or
that the transaction ended in an error condition. The TDs stalled bit is set and the active bit is
cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is
signaled to the system.
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred
for this transaction. This would generally be caused by the ICH3 not being able to access required
data buffers in memory within necessary latency requirements. Either of these conditions will
cause the C_ERR field of the TD to be decremented.
When C_ERR decrements to zero, the active bit in the TD is cleared, the stalled bit is set, the USB
error interrupt bit in the HC status register is set to 1 at the end of the frame and a hardware
interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the
incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the
C_ERR field decrements to zero, the active bit in the TD is cleared to 0, the stalled bit is set to one,
the USB error interrupt bit in the HC status register is set to 1 at the end of the frame and a
hardware interrupt is signaled to the system.
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Intel^® 82801CA ICH3-S Datasheet