82801CA Datasheet, PDF (496/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-1. Intel^® ICH3 PCI Configuration Registers (Continued)
Register Name
Offset
Datasheet Section and Location
Capability ID Register
Next Item Pointer
Power Management Capabilities
Power Management Control/Status
Register
Data Register
DCh
DDh
DE–DFh
E0–E1h
E2h
Section 7.1.20, “CAP_ID—Capability ID Register (LAN
Controller—B1:D8:F0)” on page 7-242
Section 7.1.21, “NXT_PTR—Next Item Pointer Register
(LAN Controller—B1:D8:F0)” on page 7-242
Section 7.1.22, “PM_CAP—Power Management
Capabilities Register (LAN Controller—B1:D8:F0)” on
page 7-242
Section 7.1.23, “PMCSR—Power Management Control/
Status Register (LAN Controller—B1:D8:F0)” on
page 7-243
Section 7.1.24, “PCIDATA—PCI Power Management
Data Register (LAN Controller—B1:D8:F0)” on
page 7-244
Hub Interface to PCI Bridge D30:F0
Vendor ID
Device ID
PCI Device Command Register
PCI Device Status Register
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
I/O Base Register
I/O Limit Register
Secondary Status Register
Memory Base
00–01h
02–03h
04–05h
06–07h
08h
0Ah
0Bh
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
Section 8.1.1, “VID—Vendor ID Register (HUB-PCI—
D30:F0)” on page 8-260
Section 8.1.2, “DID—Device ID Register (HUB-PCI—
D30:F0)” on page 8-260
Section 8.1.3, “CMD—Command Register (HUB-PCI—
D30:F0)” on page 8-261
Section 8.1.4, “PD_STS—Primary Device Status
Register (HUB-PCI—D30:F0)” on page 8-262
Section 8.1.5, “REVID—Revision ID Register (HUB-
PCI—D30:F0)” on page 8-263
Section 8.1.6, “SCC—Sub Class Code Register (HUB-
PCI—D30:F0)” on page 8-263
Section 8.1.7, “BCC—Base-Class Code Register (HUB-
PCI—D30:F0)” on page 8-263
Section 8.1.8, “PMLT—Primary Master Latency Timer
Register (HUB-PCI—D30:F0)” on page 8-263
Section 8.1.9, “HEADTYP—Header Type Register
(HUB-PCI—D30:F0)” on page 8-264
Section 8.1.10, “PBUS_NUM—Primary Bus Number
Register (HUB-PCI—D30:F0)” on page 8-264
Section 8.1.11, “SBUS_NUM—Secondary Bus Number
Register (HUB-PCI—D30:F0)” on page 8-264
Section 8.1.12, “SUB_BUS_NUM—Subordinate Bus
Number Register (HUB-PCI—D30:F0)” on page 8-264
Section 8.1.13, “SMLT—Secondary Master Latency
Timer Register (HUB-PCI—D30:F0)” on page 8-265
Section 8.1.14, “IOBASE—I/O Base Register (HUB-
PCI—D30:F0)” on page 8-265
Section 8.1.15, “IOLIM—I/O Limit Register (HUB-PCI—
D30:F0)” on page 8-265
Section 8.1.16, “SECSTS—Secondary Status Register
(HUB-PCI—D30:F0)” on page 8-266
Section 8.1.17, “MEMBASE—Memory Base Register
(HUB-PCI—D30:F0)” on page 8-267
496
Intel^® 82801CA ICH3-S Datasheet