82801CA Datasheet, PDF (169/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.15.3 Ultra ATA/33 Protocol
Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for each IDE
device. The IDE signal protocols are significantly different under this mode than for the 8237
mode.
Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE
controller such as the ICH3 and one or more Ultra ATA/33 capable IDE devices. It utilizes the
standard Bus Master IDE functionality and interface to initiate and control the transfer.
Ultra ATA/33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to
33 MB/s. The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16)
error checking protocol.
5.15.3.1 Signal Descriptions
The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a
number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are
shown in the following table. Read cycles are defined as transferring data from the IDE device to
the ICH3. Write cycles are defined as transferring data from ICH3 to IDE device.
Table 5-56. UltraATA/33 Control Signal Redefinitions
Standard IDE
Signal Definition
DIOW#
DIOR#
IORDY
Ultra ATA/33 Read
Cycle Definition
STOP
DMARDY#
STROBE
Ultra ATA/33 Write
Cycle Definition
STOP
STROBE
DMARDY#
ICH3 Primary
Channel Signal
PDIOW#
PDIOR#
PIORDY
ICH3 Secondary
Channel Signal
SDIOW#
SDIOR#
SIORDY
The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by
the ICH3 and is used to request that a transfer be stopped or as an acknowledgment to stop a
request from the IDE device.
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to the
ICH3 (read). It is used by the ICH3 to signal when it is ready to transfer data and to add wait-states
to the current transaction. The DIOR# signal is redefined as STROBE for transferring data from the
ICH3 to the IDE device (write). It is the data strobe signal driven by the ICH3 on which data is
transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to the ICH3
(read). It is the data strobe signal driven by the IDE device on which data is transferred during each
rising and falling edge transition. The IORDY signal is redefined as DMARDY# for transferring
data from the ICH3 to the IDE device (write). It is used by the IDE device to signal when it is ready
to transfer data and to add wait-states to the current transaction.
All other signals on the IDE connector retain their functional definitions during Ultra ATA/33
operation.
Intel^® 82801CA ICH3-S Datasheet
169