82801CA Datasheet, PDF (487/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
Testability
18
18.1 Test Mode Description
The ICH3 supports two types of test modes, a tri-state test mode and a XOR Chain test mode.
Driving RTCRST# low for a specific number of PCI clocks while PWROK is high will activate a
particular test mode as described in Table 18-1.
Note: RTCRST# can be driven low any time after PCIRST# is inactive.
.
Table 18-1. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after
PWROK active
<4
4
5
6
7
8
9–42
>42
Test Mode
No Test Mode Selected
XOR Chain 1
XOR Chain 2
XOR Chain 3
XOR Chain 4
All Z
Reserved. DO NOT ATTEMPT
No Test Mode Selected
Figure 18-1 illustrates the entry into a test mode. A particular test mode is entered upon the rising
edge of the RTCRST# after being asserted for a specific number of PCI clocks while PWROK is
active. To change test modes, the same sequence should be followed again. To restore the ICH3 to
normal operation, execute the sequence with RTCRST# being asserted so that no test mode is
selected as specified in Table 18-1.
Figure 18-1. Test Mode Entry (XOR Chain Example)
RSMRST#
PWROK
RTCRST#
Other Signal
Outputs
N Number of PCI Clocks
All Output Signals Tri-Stated
Test Mode Entered
XOR Chain Output Enabled
Intel^® 82801CA ICH3-S Datasheet
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