82801CA Datasheet, PDF (224/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.2.1 External Wake Event
Codecs can signal the controller to wake the AC-link, and wake the system using SDIN.
Figure 5-23. SDIN Wake Signaling
S YN C
Power Down
Frame
BIT_CLK
SDOUT
SDIN
slot 12
prev. frame
TAG
W rite to Data
0x20 PR4
slot 12
prev. frame
TAG
Sleep State
W ake Event
New Audio
Frame
TAG Slot 1 Slot 2
TAG Slot 1 Slot 2
SDIN W k Si
The minimum SDIN wake up pulse width is 1 µs. The rising edge of SDIN[0] or SDIN[1] causes
the ICH3 to sequence through an AC-link warm reset and set the AC97_STS bit in the GPE0_STS
Register to wake the system. The primary codec must wait to sample AC_SYNC high and low
before restarting BIT_CLK as diagrammed in Figure 5-23. The codec that signaled the wake event
must keep its SDIN high until it has sampled AC_SYNC having gone high, and then low.
The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on
the system’s current power down state. Unless a cold or register reset (a write to the reset register in
the codec) is performed, wherein the AC ’97 codec registers are initialized to their default values,
registers are required to keep state during all power down modes.
Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not
occur for a minimum of 4 audio frame times following the frame in which the power down was
triggered. When AC-link powers up, it indicates readiness via the codec ready bit.
5.18.3
AC ’97 Cold Reset
A cold reset is achieved by asserting AC_RST# for 1 µs. By driving AC_RST# low, BIT_CLK,
and SDOUT will be activated and all codec registers will be initialized to their default power on
reset values. AC_RST# is an asynchronous AC ’97 input to the codec.
5.18.4 AC ’97 Warm Reset
A warm reset will re-activate the AC-link without altering the current codec register values. A
warm reset is signaled by driving AC_SYNC high for a minimum of 1us in the absence of
BIT_CLK.
Within normal frames, AC_SYNC is a synchronous AC ’97 input to the codec. However, in the
absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the
generation of a warm reset.
The codec must not respond with the activation of BIT_CLK until AC_SYNC has been sampled
low again by the codec. This will prevent the false detection of a new frame.
Note: On receipt of wake up signalling from the codec, the digital controller will issue an interrupt if
enabled. Software will then have to issue a warm or cold reset to the codec by setting the
appropriate bit in the global control register.
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Intel^® 82801CA ICH3-S Datasheet