82801CA Datasheet, PDF (354/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.9.6
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +04h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Core
(Except bit 7 in RTC)
Bit
15:13
12
11
10
9
8
7
6:4
3
2
Description
Reserved.
HUBSERR_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH3 received an SERR# message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the SERR#.
NOTE: If this bit is set AND the SERR_EN bit in CMD Register (D30:F0, Offset 04h, bit 8) is also
set, the ICH3 will set the SSE bit in SECSTS Register (D30:F0, offset 1Eh, bit 14) AND will
also generate an NMI (or SMI# if NMI routed to SMI#).
HUBNMI_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH3 received an NMI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the NMI. .
HUBSMI_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH3 received an SMI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the SMI#.
HUBSCI_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH3 received an SCI message via the hub interface. The software must read the memory
controller hub (or its equivalent) to determine the reason for the SCI.
BIOSWR_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = ICH3 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
NOTE: On write cycles attempted to the 4MB lower alias to the BIOS space, the BIOSWR_STS
will not be set.
NEWCENTURY_STS—R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Setting this bit will cause an SMI# (but not a wake event).
Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
RTC power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit, or by other means (such as a checksum on RTC
RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a
legal value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a “1” is
written to the bit to clear it. After writing a “1” to this bit, software should not exit the SMI handler
until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
Reserved.
TIMEOUT—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by ICH3 to indicate that the SMI was caused by the TCO timer reaching 0.
TCO_INT_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.
354
Intel^® 82801CA ICH3-S Datasheet