82801CA Datasheet, PDF (171/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.15.4
Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the ICH3 supports the Ultra ATA/66 protocol. The Ultra ATA/66
protocol is enabled via configuration bits 3:0 at offset 54h. The two protocols are similar, and are
intended to be device driver compatible. The Ultra ATA/66 logic can achieve transfer rates of up to
66 MB/s.
In order to achieve the higher data rate, the timings are shortened and the quality of the cable is
improved to reduce reflections, noise, and inductive coupling. Note that the improved cable is
required and will still plug into the standard IDE connector.
The Ultra ATA/66 protocol also supports a 44 MB/s mode.
5.15.5
Ultra ATA/100 Protocol
When the ATA_FAST bit is set for any of the 4 IDE devices, then the timings for the transfers to
and from the corresponding device run at a higher rate. The ICH3 Ultra ATA/100 logic can achieve
read transfer rates up to 100 MB/s, and write transfer rates up to 88.9 MB/s.
The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further
cable improvements are required when implementing Ultra ATA/100.
5.15.6 Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed via the synchronous DMA Timing
Register and the IDE configuration register. Different timings can be programmed for each drive in
the system. The Base Clock frequency for each drive is selected in the IDE configuration register.
The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base Clock) are
programmed in the synchronous DMA timing register. The Cycle Time represents the minimum
pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the number of
Base Clock periods that the ICH3 will wait from deassertion of DMARDY# to the assertion of
STOP when it desires to stop a burst read transaction.
Note:
The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT)
must be set for 3 Base Clocks. The ICH3 will thus toggle the write strobe signal every 22.5 ns,
transferring two bytes of data on each strobe edge. This means that the ICH3 will perform Mode 5
write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe will be driven
by the ATA/100 device, and the ICH3 supports reads at the maximum rate of 100 MB/s.
Intel^® 82801CA ICH3-S Datasheet
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