82801CA Datasheet, PDF (165/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.15.2 Bus Master Function
The ICH3 can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master
channels are provided, one channel for each IDE connector (primary and secondary). By
performing the IDE data transfer as a PCI Bus master, the ICH3 off-loads the processor and
improves system performance in multitasking environments. Both devices attached to a connector
can be programmed for bus master transfers, but only one device per connector can be active at a
time.
5.15.2.1 Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region Descriptor (PRD).
The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until
all regions described by the PRDs in the table have been transferred. Note that the ICH3 bus master
IDE function does not support memory regions or Descriptor tables located on ISA.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8 bytes in
length. The first 4 bytes specify the byte address of a physical memory region. This memory region
must be dword-aligned and must not cross a 64-KB boundary. The next two bytes specify the size
or transfer count of the region in bytes (64-KB limit per region). A value of zero in these two bytes
indicates 64 KB (thus the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it
indicates that this is the final PRD in the Descriptor table. Bus master operation terminates when
the last descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base
Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of
the Base Address is not masked and if set, will cause the lower WORD byte enables to be
deasserted for the first dword transfer. The write to PCI will typically consist of a 32-byte cache
line. If valid data ends prior to end of the cache line, the byte enables will be deasserted for invalid
data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater
than the size of the disk transfer request. If greater than the disk transfer request, the driver must
terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to
0) when the drive issues an interrupt to signal transfer completion.
Figure 5-14. Physical Region Descriptor Table Entry
Main Mem ory
Byte 3
Byte 2
Byte 1
Byte 0
Mem ory Region Physical Base Address [31:1] 0
EOT
Reserved
Byte Count [15:1] 0
M em ory
Region
A single line buffer exists for the ICH3 Bus master IDE interface. This buffer is not shared with
any other function. The buffer is maintained in either the read state or the write state. Memory
writes are typically 4-dword bursts and invalid dwords have C/BE[3:0]#=0Fh. The line buffer
allows burst data transfers to proceed at peak transfer rates.
Intel^® 82801CA ICH3-S Datasheet
165