82801CA Datasheet, PDF (338/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Bit
Description
Power Button Status (PWRBTN__STS)—R/WC. This bit is not affected by hard resets caused by a
CF9 write.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the
PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state
with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
8 ¹⁼
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any
other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if
SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN and PWRBTN_STS are both set, a wake
event is generated.
7:6 Reserved.
Global Status (GBL _STS)—R/WC.
5 ^{0 = The SCI handler should then clear this bit by writing a 1 to the bit location.}
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has
a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.
4:1 Reserved.
Timer Overflow Status (TMROF_STS)—R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
0 _{1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).}
This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the
TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
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Intel^® 82801CA ICH3-S Datasheet