82801CA Datasheet, PDF (423/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.2.2
13.2.3
x_CIV—Current Index Value Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 04h (PICIV),
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
00h
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32-bit read from address offset 04h. Software can also read this register individually by doing a
single 8-bit read to offset 04h.
Bit
Description
7:5 Hardwired to 0.
Current Index Value[4:0]—RO. These bits represent which buffer descriptor within the list of 32
4:0 descriptors is currently being processed. As each descriptor is processed, this value is
incremented. The value rolls over after it reaches 31.
x_LVI—Last Valid Index Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 05h (PILVI),
NABMBAR + 15h (POLVI),
NABMBAR + 25h (MCLVI)
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32 bit read from address offset 04h. Software can also read this register individually by doing a
single 8 bit read to offset 05h.
Bit
Description
7:5 Hardwired to 0.
4:0
Last Valid Index[4:0]—R/W. This value represents the last valid descriptor in the list. This value is
updated by the software each time it prepares a new buffer and adds it to the list.
Intel^® 82801CA ICH3-S Datasheet
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