82801CA Datasheet, PDF (8/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

5.8.4 PCI Message-Based Interrupts....................................................... 121
5.8.4.1 Theory of Operation ........................................................ 121
5.8.4.2 Registers and Bits Associated with PCI Interrupt
Delivery ........................................................................... 121
5.8.5 Processor System Bus Interrupt Delivery ....................................... 122
5.8.5.1 Theory of Operation ........................................................ 122
5.8.5.2 Edge-Triggered Operation............................................... 122
5.8.5.3 Level-Triggered Operation .............................................. 122
5.8.5.4 Registers Associated with Processor System Bus
Interrupt Delivery ............................................................. 122
5.8.5.5 Interrupt Message Format ............................................... 123
5.9 Serial Interrupt (D31:F0) .............................................................................. 124
5.9.1 Start Frame..................................................................................... 124
5.9.2 Data Frames ................................................................................... 125
5.9.3 Stop Frame ..................................................................................... 125
5.9.4 Specific Interrupts not Supported via SERIRQ ............................... 125
5.9.5 Data Frame Format ........................................................................ 126
5.10 Real Time Clock (D31:F0) ........................................................................... 127
5.10.1 Update Cycles ................................................................................ 127
5.10.2 Interrupts......................................................................................... 128
5.10.3 Lockable RAM Ranges ................................................................... 128
5.10.4 Century Rollover ............................................................................. 128
5.10.5 Clearing Battery-Backed RTC RAM................................................ 128
5.11 Processor Interface (D31:F0) ...................................................................... 130
5.11.1 Processor Interface Signals ............................................................ 130
5.11.1.1 A20M# ............................................................................. 130
5.11.1.2 INIT#................................................................................ 130
5.11.1.3 FERR#/IGNNE# (Coprocessor Error) ............................. 131
5.11.1.4 NMI.................................................................................. 132
5.11.1.5 STPCLK# and CPUSLP# Signals ................................... 132
5.11.1.6 CPUPWRGD Signal ........................................................ 132
5.11.2 Dual Processor Issues .................................................................... 132
5.11.2.1 Signal Differences ........................................................... 132
5.11.2.2 Power Management ........................................................ 132
5.11.3 Speed Strapping for the Processor................................................. 133
5.12 Power Management (D31:F0) ..................................................................... 134
5.12.1 Features.......................................................................................... 134
5.12.2 Intel^® ICH3 and System Power States ........................................... 135
5.12.3 System Power Planes..................................................................... 137
5.12.4 Intel^® ICH3 Power Planes............................................................... 137
5.12.5 SMI#/SCI Generation...................................................................... 137
5.12.6 Dynamic Processor Clock Control .................................................. 140
5.12.6.1 Throttling Using STPCLK# .............................................. 141
5.12.6.2 Transition Rules Among S0/Cx and Throttling States ..... 142
5.12.7 Sleep States ................................................................................... 142
5.12.7.1 Initiating Sleep State ....................................................... 143
5.12.7.2 Exiting Sleep States ........................................................ 143
5.12.7.3 Sx–G3–Sx, Handling Power Failures .............................. 145
5.12.8 Thermal Management..................................................................... 146
5.12.8.1 THRM# Signal ................................................................. 146
5.12.8.2 THRM# Initiated Passive Cooling.................................... 146
5.12.8.3 THRM# Override Software Bit......................................... 146
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Intel^® 82801CA ICH3-S Datasheet