82801CA Datasheet, PDF (132/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.11.1.4 NMI
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-31.
Table 5-31. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally, externally
via SERR# signal, or via message from MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4Eh, bit 11).
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4Eh, bit 11).
5.11.1.5
STPCLK# and CPUSLP# Signals
The ICH3 power management logic controls these active-low signals. Refer to Section 5.12 for
more information on the functionality of these signals.
5.11.1.6
CPUPWRGD Signal
This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal
(external pull-up resistor required) that represents a logical AND of the ICH3’s PWROK and
VRMPWRGD signals.
5.11.2 Dual Processor Issues
5.11.2.1 Signal Differences
In dual processor designs, some of the processor signals are unused or used differently than for
uniprocessor designs.
Table 5-32. DP Signal Differences
Signal
Difference
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Generally not used, but still supported by ICH3.
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both CPUs.
Generally not used, but still supported by ICH3.
5.11.2.2
Power Management
Attempting clock control with more than one processor is not feasible, because the Host controller
does not provide any indication as to which processor is executing a particular Stop-Grant cycle.
Without this information, there is no way for the ICH3 to know when it is safe to deassert
STPCLK#.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected
to both processors. However, for ACPI implementations, the ICH3 will not support the C2 state for
both processors, since there are not two processor control blocks. The BIOS must indicate that the
ICH3 only supports the C1 state for dual processor designs. However, the THRM# signal can be
used for overheat conditions to activate thermal throttling.
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Intel^® 82801CA ICH3-S Datasheet