82801CA Datasheet, PDF (174/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-59. TD Control and Status
Bit
31:30
29
Description
Reserved.
Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet, is
in a queue; and successfully completes with an actual length less than the maximum length, then
the TD is marked inactive, the Queue Header is not updated and the USBINT status bit (status
register) is set at the end of the frame. In addition, if the interrupt is enabled, the interrupt will be sent
at the end of the frame.
Note that any error (e.g., babble or FIFO error) prevents the short packet from being reported. The
behavior is undefined when this bit is set with output packets or packets outside of queues.
0 = Disable.
1 = Enable.
Error Counter (C_ERR). This field is a 2-bit down counter that keeps track of the number of Errors
detected while executing this TD. If this field is programmed with a non zero value during setup, the
ICH3 decrements the count and writes it back to the TD if the transaction fails. If the counter counts
from one to zero, the ICH3 marks the TD inactive, sets the “STALLED” and error status bit for the
error that caused the transition to zero in the TD. An interrupt will be generated to Host Controller
Driver (HCD) if the decrement to zero was caused by Data Buffer error, Bit stuff error, or if enabled,
a CRC or Timeout error. If HCD programs this field to zero during setup, the ICH3 will not count
errors for this TD and there will be no limit on the retries of this TD.
28:27
Bits[28:27]
00
01
10
11
Interrupt After
No Error Limit
Error
2 Errors
3 Errors
Error
Decrement Counter
Error
Decrement Counter
CRC Error
Yes
Data Buffer Error
Yes
Timeout Error
Yes
Stalled
No*
NAK Received
No
Bit stuff Error
Yes
Babble Detected No*
*Detection of Babble or Stall automatically deactivates the TD. Thus, count is not decremented.
Low Speed Device (LS). This bit indicates that the target device (USB data source or sink) is a low
speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/sec). There are special
restrictions on schedule placement for low speed TDs. If an ICH3 root hub port is connected to a full
speed device and this bit is set to a 1 for a low speed transaction, the ICH3 sends out a low speed
26 _{preamble on that port before sending the PID. No preamble is sent if a ICH3 root hub port is}
connected to a low speed device.
0 = Full Speed Device
1 = Low Speed Device
Isochronous Select (IOS). The field specifies the type of the data structure. If this bit is set to a 1,
then the TD is an isochronous transfer. Isochronous TDs are always marked inactive by the
25 ^{hardware after execution, regardless of the results of the transaction.}
0 = Non-isochronous Transfer Descriptor
1 = Isochronous Transfer Descriptor
Interrupt on Complete (IOC). This specifies that the ICH3 should issue an interrupt on completion
of the frame in which this Transfer Descriptor is executed. Even if the active bit in the TD is already
24 ^{cleared when the TD is fetched (no transaction will occur on USB), an IOC interrupt is generated at}
the end of the frame.
1 = Issue IOC
Active. For ICH3 schedule execution operations, see the Data Transfers To/From Main Memory
section.
23 ^{0 = When the transaction associated with this descriptor is completed, the ICH3 sets this bit to 0}
indicating that the descriptor should not be executed when it is next encountered in the
schedule. The active bit is also set to 0 if a stall handshake is received from the endpoint.
1 = Set to 1 by software to enable the execution of a message transaction by the ICH3.
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Intel^® 82801CA ICH3-S Datasheet