82801CA Datasheet, PDF (251/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.2.6
7.2.7
Management Data Interface (MDI) Control Register
Offset Address: 10–13h
Default Value: 0000 0000h
Attribute:
Size:
R/W (special)
32 bits
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and
write bits from the LAN Connect component. This register may be written as a 32-bit entity, two
16-bit entities, or four 8-bit entities. The LAN Controller will only accept the command after the
high byte (offset 13h) is written, therefore the high byte must be written last.
Bit
Description
31:30
29
28
27:26
25:21
20:16
15:0
These bits are reserved and should be set to 00b.
Interrupt Enable.
0 = Disable.
1 = Enables the LAN Controller to assert an interrupt to indicate the end of an MDI cycle.
Ready.
0 = Expected to be reset by software at the same time the command is written.
1 = Set by the LAN Controller at the end of an MDI transaction.
Opcode. These bits define the opcode:
00 = Reserved
01 = MDI write
10 = MDI read
11 = Reserved
LAN Connect Address. This field of bits contains the LAN Connect address.
LAN Connect Register Address. This field of bits contains the LAN Connect Register Address.
Data. In a write command, software places the data bits in this field, and the LAN Controller
transfers the data to the external LAN Connect component. During a read command, the LAN
Controller reads these bits serially from the LAN Connect, and software reads the data from this
location.
Receive DMA Byte Count Register
Offset Address: 14–17h
Default Value: 0000 0000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:0
Receive DMA Byte Count—RO. Keeps track of how many bytes of receive data have been passed
into host memory via DMA.
Intel^® 82801CA ICH3-S Datasheet
251