82801CA Datasheet, PDF (373/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
Bit
Description
Drive 0 DMA Timing Enable (DTE0)—R/W.
3
0 = Disable.
1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
port will run in compatible timing.
Drive 0 Prefetch/Posting Enable (PPE0)—R/W.
2
0 = Disable prefetch and posting to the IDE data port for this drive.
1 = Enable prefetch and posting to the IDE data port for this drive.
Drive 0 IORDY Sample Point Enable (IE0)—R/W.
1
0 = Disable IORDY sampling is disabled for this drive.
1 = Enable IORDY sampling for this drive.
Drive 0 Fast Timing Bank (TIME0)—R/W.
0
0 = Accesses to the data port will use compatible timings for this drive.
1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the
recovery time.
10.1.21
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)
Address Offset: 44h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Secondary Drive 1 IORDY Sample Point (SISP1)—R/W. Determines the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data
port and bit 14 of the IDE timing register for secondary is set.
7:6 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Secondary Drive 1 Recovery Time (SRCT1)—R/W. Determines the minimum number of PCI clocks
between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to
drive 1 data port and bit 14 of the IDE timing register for secondary is set.
5:4 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Primary Drive 1 IORDY Sample Point (PISP1)—R/W. Determines the number of PCI clocks
between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port
and bit 14 of the IDE timing register for primary is set.
3:2 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1)—R/W. Determines the minimum number of PCI clocks
between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to
drive 1 data port and bit 14 of the IDE timing register for primary is set.
1:0 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Intel^® 82801CA ICH3-S Datasheet
373