82801CA Datasheet, PDF (46/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
Table 2-10. Power Management Interface Signals (Continued)
Name
RI#
RSMRST#
LAN_RST#
SUS_STAT#
SUSCLK
VRMPWRGD
Type
I
I
I
O
O
I
Description
Ring Indicate: From the modem interface. Can be enabled as a wake event,
and this is preserved across power failures.
Resume Well Reset: Used for resetting the resume power plane logic.
LAN Reset: This signal must be asserted at least 10 ms after the resume well
power (VccSus3_3 and VccSus1_8 ) is valid. When deasserted, this signal is an
indication that the resume well power is stable.
Suspend Status: This signal is asserted by the ICH3 to indicate that the system
will be entering a low power state soon. This can be monitored by devices with
memory that need to switch from normal refresh to suspend refresh mode. It can
also be used by other peripherals as an indication that they should isolate their
outputs that may be going to powered-off planes.
Suspend Clock: Output of the RTC generator circuit to use by other chips for
refresh clock.
VRM Power Good: This should be connected to be the processor’s VRM Power
Good.
2.11 Processor Interface
Table 2-11. Processor Interface Signals
Name
A20M#
CPUSLP#
FERR#
IGNNE#
Type
O
O
I
O
Description
Mask A20: A20M# will go active based on either setting the appropriate bit in
the Port 92h register, or based on the A20GATE input being active.
Speed Strap: During the reset sequence, ICH3 drives A20M# high if the
corresponding bit is set in the FREQ_STRP Register.
CPU Sleep: This signal puts the processor into a state that saves substantial
power compared to Stop-Grant state. However, during that time, no snoops
occur. The ICH3 can optionally assert the CPUSLP# signal when going to the
S1 state.
Numeric Coprocessor Error: This signal is tied to the coprocessor error signal
on the processor. FERR# is only used if the ICH3 coprocessor error reporting
function is enabled in the General Control Register (Device 31:Function 0,
Offset D0, bit 13). If FERR# is asserted, the ICH3 generates an internal IRQ13
to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure
that IGNNE# is not asserted to the processor unless FERR# is active. FERR#
requires an external weak pull-up to ensure a high level when the coprocessor
error function is disabled.
NOTE: FERR# can be used in some states for notification by the processor of
pending interrupt events (this functionality is independent of the
General Control Register bit setting).
Ignore Numeric Error: This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the ICH3 coprocessor error reporting function
is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit
13). If FERR# is active, indicating a coprocessor error, a write to the
Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE#
remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
Speed Strap: During the reset sequence, ICH3 drives IGNNE# high if the
corresponding bit is set in the FREQ_STRP Register.
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Intel^® 82801CA ICH3-S Datasheet