82801CA Datasheet, PDF (269/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.24
BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)
Offset Address: 3E–3Fh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:8 Reserved.
7
Fast Back to Back Enable—RO. Hardwired to 0. The PCI logic will not generate fast back-to-back
cycles on the PCI bus.
6
Secondary Bus Reset—RO. hardwired to 0. The ICH3 does not follow the P2P bridge reset scheme;
Software-controlled resets are implemented in the PCI-LPC device.
Master Abort Mode—R/W. This bit controls the behavior of the ICH3 when a master abort occurs on
a transaction that crosses the hub interface-PCI bridge in either direction. The default is 0.
When set to 0, the ICH3 behaves in the following manner:
• Hub Interface Completion-Required requests to PCI: When these master abort on PCI, the
ICH3 returns a master abort status. For reads, FFFFh is returned for each DWord.
• Hub Interface Posted Writes to PCI: When these master abort on PCI, the ICH3 discards the
data.
• PCI Reads to Hub Interface: When these master abort on Hub Interface, the ICH3 returns the
data provided with the Hub Interface master abort packet to the PCI requestor.
5
• PCI writes to Hub Interface: The ICH3 has no idea when these "master-abort."
When set to 1, the ICH3 treats the master abort as an error:
• Hub Interface Completion-Required requests to PCI: When these master abort on PCI, the
ICH3 returns a target abort status. For reads, FFFFh is returned for each DWord.
• Hub Interface Posted Writes to PCI: When these master abort on PCI, the ICH3 discards the
data and sets the Primary Signaled SERR# bit (if the corresponding SERR_EN bit is set).
• PCI Reads to Hub Interface: When these master abort on Hub Interface, the ICH3 terminates
the cycle with a target abort and flushes the remainder of the prefetched data.
• PCI writes to Hub Interface: the ICH3 has no idea when these "master-abort."
VGA 16-Bit Decode. This bit does not have any functionality relative to address decodes because
4
the ICH3 will forward the cycles to PCI, independent of the decode. Writes of 1 have no impact other
than to force the bit to 1. Writes of 0 have no impact other than to force the bit to 0. Reads to this bit
will return the previously written value (or 0 if no writes since reset).
VGA Enable—R/W.
0 = No VGA device on PCI.
3 _{1 = Indicates that the VGA device is on PCI. Therefore, the PCI to hub interface decoder will not}
accept memory cycles in the range A0000h–BFFFFh. Note that the ICH3 will never take I/O
cycles in the VGA range from PCI.
ISA Enable—R/W. The ICH3 ignores this bit. However, this bit is read/write for software compatibility.
2 Since the ICH3 forwards all I/O cycles that are not in the USB, AC ’97, or IDE ranges to PCI, this bit
would have no effect.
SERR# Enable—R/W.
0 = Disable
1 _{1 = If this bit is set AND bit 8 in CMD register (D30:F0 Offset 04h) is also set, the ICH3 will set the}
SSE bit in PD_STS register (D30:F0, offset 06h, bit 14) AND also generate an NMI (or SMI# if
NMI routed to SMI) when the SERR# signal is asserted.
Parity Error Response Enable—R/W.
0 _{0 = Disable}
1 = Enable the hub interface to PCI bridge for parity error detection and reporting on the PCI bus.0 =
Intel^® 82801CA ICH3-S Datasheet
269