82801CA Datasheet, PDF (467/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Electrical Characteristics
Table 16-10. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
Sym
Parameter¹
t80 Sustained Cycle Time (T2cyctyp)
t81 Cycle Time (Tcyc)
t82 Two Cycle Time (T2cyc)
t83a Data Setup Time (Tds)
t84a Data Hold Time (Tdh)
t85a Data Valid Setup Time (Tdvs)
t86a Data Valid Hold Time (Tdvh)
t87 Limited Interlock Time (Tli)
t88 Interlock Time w/ Minimum (Tmli)
t89 Envelope Time (Tenv)
t90 Ready to Pause Time (Trp)
t91 DMACK setup/hold Time (Tack)
t92a
CRC Word Setup Time at Host
(Tcvs)
CRC word valid hold time at
t92b
sender (from DMACK# negation
until CRC may become invalid)²
(Tcvh)
STROBE output released-to-
t93 driving to the first transition of
critical timing (Tzfs)
Data Output Released-to-Driving
t94 Until the First Tunisian of Critical
Timing (Tdzfs)
t95 Unlimited Interlock Time (Tui)
Maximum time allowed for output
t96a drivers to release (from asserted
or negated) (Taz)
t96b
Minimum time for drivers to assert
or negate (from released) (Tzad)
Ready-to-final-STROBE time (no
t97
STROBE edges shall be sent this
long after negation of DMARDY#)
(Trfs)
Mode 0
(ns)
Min Max
Mode 1
(ns)
Min Max
Mode 2
(ns)
Min Max
Measuring
Location
Figure
240
112
230
15
5
70
6.2
0 150
20
20 70
160
20
70
160
73
153
10
5
48
6.2
0 150
20
20 70
125
20
48
120
54
115
7
5
31
6.2
0 150
20
20 70
100
20
31
Sender
Connector
End
Recipient 16-10
Connector
Sender
Connector
16-10
Recipient
Connector
16-10
Recipient
Connector
16-10
Sender
Connector
16-10
Sender
Connector
16-10
See Note 2 16-12
Host
Connector
16-12
Host
Connector
16-9
Recipient
Connector
16-11
Host 16-9,
Connector 16-12
Host
Connector
6.2
6.2
6.2
Host
Connector
0
0
0
Device
Connector
70
48
31
Sender
Connector
0
0
0
Host
Connector
10
10
10 See Note 2
0
0
0
Device
Connector
75
70
60
Sender
Connector
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