82801CA Datasheet, PDF (87/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR)
The ICH3 will always drive bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-4 shows the valid bit encodings.
Table 5-4. Cycle Type Bit Definitions
Bits[3:2]
00
00
01
01
10
10
11
Bit[1]
0
1
0
1
0
1
x
Definition
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this value, the
ICH3 will abort the cycle.
5.3.1.4 SIZE
Bits[3:2] are reserved. The ICH3 will always drive them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, the ICH3 will ignore those bits.
Table 5-5 shows the encoding for Bits[1:0].
Table 5-5. Transfer Size Bit Definition
Bits[1:0]
Size
00
8-bit transfer (1 byte)
01
16-bit transfer (2 bytes)
10
Reserved. The ICH3 never drives this combination. If a peripheral running a bus master
cycle drives this combination, the ICH3 may abort the transfer.
11
32-bit transfer (4 bytes)
Intel^® 82801CA ICH3-S Datasheet
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