82801CA Datasheet, PDF (45/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.9
USB Interface
Table 2-9. USB Interface Signals
Name
USBP0P,
USBP0N,
USBP1P,
USBP1N
USBP2P,
USBP2N,
USBP3P,
USBP3N
USBP4P,
USBP4N,
USBP5P,
USBP5N
OC[5:0]#
USBRBIAS
Type
I/O
I/O
I/O
I
I
Description
Universal Serial Bus Port 1:0 Differential: These differential pairs are used to
transmit Data/Address/Command signals for ports 0 and 1. These ports are
routed to USB 1.1 Controller #1.
NOTE: No external resistors are required on these signals. The ICH3
integrates 15 kΩ pull-downs and provides an effective output driver
impedance of 45 Ω which requires no external series resistor.
Universal Serial Bus Port 3:2 Differential: These differential pairs are used to
transmit Data/Address/Command signals for ports 2 and 3. These ports are
routed to USB 1.1 Controller #2.
NOTE: No external resistors are required on these signals. The ICH3
integrates 15 kΩ pull-downs and provides an effective output driver
impedance of 45 Ω which requires no external series resistor.
Universal Serial Bus Port 5:4 Differential: These differential pairs are used to
transmit Data/Address/Command signals for ports 4 and 5. These ports are
routed to USB 1.1 Controller #3.
NOTE: No external resistors are required on these signals. The ICH3
integrates 15 kΩ pull-downs and provides an effective output driver
impedance of 45 Ω that requires no external series resistor.
Overcurrent Indicators: These signals set corresponding bits in the USB
controllers to indicate that an overcurrent condition has occurred.
USB Resistor Bias: Analog connection for an external 18.2 Ω resistor (± 1%)
to ground, used to set transmit current and internal load resistors.
2.10 Power Management Interface
Table 2-10. Power Management Interface Signals
Name
THRM#
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
Type
I
O
O
I
I
Description
Thermal Alarm: Active low signal generated by external hardware to start the
Hardware clock throttling mode. Can also generate an SMI# or an SCI.
S3 Sleep Control: Power plane control. Shuts off power to all non-critical
systems when transistioning to S3 (Suspend To RAM), S4 (Suspend to Disk) or
S5 (Soft Off) states.
S5 Sleep Control: Power plane control. The signal is used to shut power off to
all non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states.
Power OK: When asserted, PWROK is an indication to the ICH3 that core
power and PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, the ICH3 asserts PCIRST#.
NOTE: PWROK must deassert for a minimum of 3 RTC clock periods in order
for the ICH3 to fully reset the power and properly generate the
PCIRST# output
Power Button: The Power Button will cause SMI# or SCI to indicate a system
request to go to a sleep state. If the system is already in a sleep state, this signal
will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this
will cause an unconditional transition (power button override) to the S5 state with
only the PWRBTN# available as a wake event. Override will occur even if the
system is in the S1–S4 states. This signal has an internal pull-up resistor.
Intel^® 82801CA ICH3-S Datasheet
45