82801CA Datasheet, PDF (408/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.7
12.2.8
)
12.2.9
BLOCK_DB—Block Data Byte Register
Register Offset: 07h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Block Data Byte—R/W. For Block Writes, the software will write the first byte to this register as part
of the setup for this command. After the ICH3 has sent the Address, Command, and Byte Count
fields, it will send the byte in the Block Data Byte register. After the byte has been sent, the ICH3 will
set the BYTE_DONE_STS bit in the Host Status register. If there are more bytes to send, the software
then writes the next byte to the Block Data Byte register and subsequently clears the
BYTE_DONE_STS bit. The ICH3 will then send the next byte. During the time from when a byte has
been transmitted to when the next byte has been loaded, the ICH3 will insert wait-states on the
7:0 _SMBus/I2_C.
A similar process will be used for Block Reads. After receiving the byte count (which goes in the DATA
0 register), the first “data byte” goes in the Block Data Byte register and the ICH3 will generate an
SMI# or interrupt (depending on configuration). The interrupt or SMI# handler will then read the byte
and clear the BYTE_DONE_STS bit. This will free room for the next byte. During the time from when
a byte is read to when the BYTE_DONE_STS bit is cleared, the ICH3 will insert wait-states on the
SMBus/I ²C.
PEC—Packet Error Check (PEC) Register
Register Offset: 08h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
PEC_DATA—R/W. This 8-bit register is written with the 8-bit CRC value that is used as the SMBus
PEC data prior to a write transaction. For read transactions, the PEC data is loaded from the SMBus
7:0 into this register and is then read by software. Software must ensure that the INUSE_STS bit is
properly maintained to avoid having this field over-written by a write transaction following a read
transaction.
RCV_SLVA—Receive Slave Address Register
Register Offset: 09h
Default Value: 44h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
7
6:0
Description
Reserved.
SLAVE_ADDR—R/W. This field is the slave address that the ICH3 decodes for read and write cycles.
the default is not 0, so the SMBus Slave Interface can respond even before the processor comes up
(or if the processor is dead). This register is cleared by RSMRST#, but not by PCIRST#.
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Intel^® 82801CA ICH3-S Datasheet