82801CA Datasheet, PDF (417/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.1.10
NAMBAR—Native Audio Mixer Base Address Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
10–13h
00000001h
No
Attribute:
Size:
Power Well:
R/W
32 bits
Core
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous
block of I/O space that is to be used for the Native Audio Mixer software interface. The mixer
requires 256 bytes of I/O space. Native Audio Mixer and Modem codec I/O registers are located
from 00h to 7Fh and reside in the codec. Access to these registers will be decoded by the AC ’97
controller and forwarded over the AC-link to the codec. The codec will then respond with the
register value.
In the case of the split codec implementation, accesses to the different codecs are differentiated by
the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh
for the secondary codec.
For description of these I/O registers, refer to the Audio Codec ’97, Revision 2.2 specification.
Bit
Description
31:16
15:8
7:1
0
Hardwired to 0s.
Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Mixer
interface registers. The number of upper bits that a device actually implements depends on how
much of the address space the device will respond to. For the AC ’97 mixer, the upper 16 bits are
hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block
size of 256 bytes for this base address.
Reserved. Read as 0s.
Resource Type Indicator (RTE)—RO. Hardwired to 1, indicating a request for I/O space.
13.1.11
NABMBAR—Native Audio Bus Mastering Base Address
Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
14–17h
00000001h
No
Attribute:
Size:
Power Well:
R/W
32 bits
Core
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous
block of I/O space that is to be used for the Native Mode Audio software interface.
Bit
31:16
15:6
5:1
0
Description
Hardwired to 0s.
Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Bus
Mastering interface registers. The number of upper bits that a device actually implements depends
on how much of the address space the device will respond to. For AC ’97 bus mastering, the upper
16 bits are hardwired to 0, while bits 15:6 are programmable. This configuration yields a maximum
I/O block size of 64 bytes for this base address.
Reserved. Read as 0s.
Resource Type Indicator (RTE)—RO. This bit is set to one, indicating a request for I/O space.
Intel^® 82801CA ICH3-S Datasheet
417