82801CA Datasheet, PDF (281/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.12
9.1.13
BIOS_CNTL Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
4E–4Fh
0000h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:2 Reserved.
BIOS Lock Enable (BLE)—R/W.
1
0 = Setting the BIOSWE will not cause SMIs. Once set, this bit can only be cleared by a
PCIRST#.
1 = Enables setting the BIOSWE bit to cause SMIs.
BIOS Write Enable (BIOSWE)—R/W.
0 = Only read cycles result in FWH I/F cycles.
0
1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written
from a 0 to a 1 and BIOS lock Enable (BLE) is also set, an SMI# is generated. This ensures
that only SMM code can update BIOS.
TCO_CNTL—TCO Control Register (LPC I/F—D31:F0)
Offset Address: 54h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:4 Reserved.
TCO Interrupt Enable (TCO_INT_EN)—R/W. This bit enables/disables the TCO interrupt.
3
0 = Disables TCO interrupt.
1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL field.
TCO Interrupt Select (TCO_INT_SEL)—R/W. Specifies on which IRQ the TCO will internally
appear. If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not
sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the
TCO interrupt can also be mapped to IRQ20–23, and can be shared with other interrupt. Note that
if the TCOSCI_EN bit is set (bit 6 of the GPEO_EN register), then the TCO interrupt will be sent to
the same interrupt as the SCI, and the TCO_INT_SEL bits will have no meaning. When the TCO
interrupt is mapped to APIC interrupts 9, 10 or 11, the signal is in fact active high. When the TCO
interrupt is mapped to IRQ 20, 21, 22, or 23, the signal is active low and can be shared with PCI
interrupts that may be mapped to those same signals (IRQs).
2:0
Bits
SCI Map
000
IRQ9
001
IRQ10
010
IRQ11
011
Reserved
100
IRQ20 (Only available if APIC enabled)
101
IRQ21 (Only available if APIC enabled)
110
IRQ22 (Only available if APIC enabled)
111
IRQ23 (Only available if APIC enabled)
Intel^® 82801CA ICH3-S Datasheet
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