82801CA Datasheet, PDF (355/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.9.7
Bit
Description
SW_TCO_SMI—R/WC.
1
0 = Software clears this bit by writing a 1 to the bit position.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register.
NMI2SMI_STS—RO.
0
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the ICH3 when an SMI# occurs because an event occurred that would otherwise have
caused an NMI (because NMI2SMI_EN is set).
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +06h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Resume
(Except Bit 0, in RTC)
Bit
Description
15:5 Reserved.
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS)—R/W. (Allow the software to go directly into
pre-determined sleep state. This avoids race conditions.
4 ^{0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3–S5}
states.
1 = ICH3 sets this bit to 1 when it receives the SMI message on the SMLink's Slave Interface.
Software clears the bit by writing a 1 to this bit position.
3 Reserved.
BOOT_STS.
0 = Cleared by ICH3 based on RSMRST# or by software writing a 1 to this bit. Note that software
should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit.
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the
2
first instruction.
NOTE: If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the ICH3 will
reboot using the ‘safe’ multiplier (1111). This allows the system to recover from a processor
frequency multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot.
If the bit is set and the frequency multiplier is 1111, then the BIOS knows that the processor
has been programmed to an illegal multiplier.
SECOND_TO_STS—R/WC.
0 = This bit is cleared by writing a 1 to the bit position or by a RSMRST#.
1
1 = The ICH3 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably due
to system lock). If this bit is set and the NO_REBOOT configuration bit is 0, then the ICH3 will
reboot the system after the second timeout. The reboot is done by asserting PCIRST#.
0=
Intruder Detect (INTRD_DET)—R/WC.
0 ^{0 = This bit is only cleared by writing a 1 to the bit position, or by RTCRST# assertion.}
1 = Set by ICH3 to indicate that an intrusion was detected. This bit is set even if the system is in G3
state.
Intel^® 82801CA ICH3-S Datasheet
355