82801CA Datasheet, PDF (285/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.20
9.1.21
D31_ERR_STS—Device 31 Error Status Register
(LPC I/F—D31:F0)
Offset Address: 8Ah
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/WC
8-bit
Core
This register configures the ICH3’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register.
Bit
Description
7:3 Reserved.
SERR# Due to Received Target Abort (SERR_RTA)—R/WC.
2 ^{0 = Software clears this bit by writing a 1 to the bit location.}
1 = The ICH3 sets this bit when it receives a target abort. If SERR_EN, the ICH3 will also generate
an SERR# when SERR_RTA is set.
SERR# Due to Delayed Transaction Timeout (SERR_DTT)—R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 _{1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH3}
clears the delayed transaction and sets this bit. If both SERR_DTT_EN and SERR_EN are set,
then ICH3 will also generate an SERR# when SERR_DTT is set.
0 Reserved.
PCI_DMA_CFG—PCI DMA Configuration Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
90h–91h
0000h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Channel 7 Select—R/W.
00 = Reserved
01 = PC/PCI DMA
10 = Reserved
11 = LPC I/F DMA
Channel 6 Select—R/W. Same bit decode as for Channel 7.
Channel 5 Select—R/W. Same bit decode as for Channel 7.
Reserved.
Channel 3 Select—R/W. Same bit decode as for Channel 7.
Channel 2 Select—R/W. Same bit decode as for Channel 7.
Channel 1 Select—R/W. Same bit decode as for Channel 7.
Channel 0 Select—R/W. Same bit decode as for Channel 7.
Intel^® 82801CA ICH3-S Datasheet
285