82801CA Datasheet, PDF (205/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.17.4 Interrupts / SMI#
The ICH3 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN
bit.
Table 5-89 and Table 5-90 specify how the various enable bits in the SMBus function control the
generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables
are additive, which means that if more than one row is true for a particular scenario then the Results
for all of the activated rows will occur.
Table 5-88. Enable for SMBALERT#
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration Register,
D31:F3:Offset 40h, Bit 1)
SMBALERT_DIS
(Slave Command
I/O Register, Offset
11h, Bit 2)
Result
X
X
SMBALERT#
asserted low
(always reported
X
1
in Host Status
Register, Bit 5)
1
0
X
Wake generated
Slave SMI#
0
generated
(SMBUS_SMI_S
TS)
0
Interrupt
generated
Table 5-89. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host Control
I/O Register, Offset
02h, Bit 0)
SMB_SMI_EN
(Host Configuration
Register, D31:F3:Offset
40h, Bit1)
Result
Slave Write to Wake/
SMI# Command
X
Slave Write to
SMLINK_SLAVE_SMI
X
Command
0
Any combination of
Host Status Register
1
[4:1] asserted
1
Wake generated when asleep.
X
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when in
X
the S0 state
(SMBUS_SMI_STS)
X
None
0
Interrupt generated
1
Host SMI# generated
Table 5-90. Enables for the Host Notify Command
HOST_NOTIFY_INTREN SMB_SMI_EN (Host
HOST_NOTIFY_WKEN
(Slave Control I/O
Configuration Register,
(Slave Control I/O
Register, Offset 11h, Bit 0) D31:F3:Off40h, Bit 1) Register, Offset 11h, Bit 1)
Result
0
X
0
None
X
X
1
Wake generated
1
0
X
Interrupt generated
1
1
X
Slave SMI# generated
(SMBUS_SMI_STS)
Intel^® 82801CA ICH3-S Datasheet
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