82801CA Datasheet, PDF (151/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.10.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for the PIC to
operate properly. Therefore, there is no need to return these values in ALT access mode. When
reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in the
following table.
Table 5-47. PIC Reserved Bits Return Values
PIC Reserved Bits
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
OCW2(4:3)
OCW3(7)
OCW3(5)
OCW3(4:3)
Value Returned
000
000
00
0
00
0
Reflects bit 6
01
5.12.10.3 Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-48 have write paths to them in ALT access mode. Software will
restore these values after returning from a powered down state. These registers must be handled
special by software. When in normal mode, writing to the base address/count register also writes to
the current address/count register. Therefore, the base address/count must be written first, then the
part is put into ALT access mode and the current address/count register is written.
Table 5-48. Register Write Accesses in ALT Access Mode
I/O Address
Register Write Value
08h
DMA Status Register for channels 0–3.
D0h
DMA Status Register for channels 4–7.
Intel^® 82801CA ICH3-S Datasheet
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