82801CA Datasheet, PDF (49/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.15 Other Clocks
Table 2-15. Other Clocks
Name
CLK14
CLK48
CLK66
Type
Description
I
Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. This clock is
permitted to stop during S3 (or lower) states .
I
48 MHz Clock: Used to run the USB controller. Runs at 48 MHz. This clock is
permitted to stop during S3 (or lower) states.
I
66 MHz Clock: Used to run the hub interface. Runs at 66 MHz. This clock is
permitted to stop during S3 (or lower) states .
2.16 Miscellaneous Signals
Table 2-16. Miscellaneous Signals
Name
SPKR
RTCRST#
TP[0]
Type
Description
Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with
Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external
speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its
O ^{output state is 0.}
NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See
Section 2.20.1for more details. There is a weak integrated pull-down
resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC well and sets
the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 Register).
NOTES:
I
1. Clearing CMOS in an ICH3-based platform can be done by using a jumper on
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low. Unless entering
the XOR Chain Test Mode, the RTCRST# input must always be high when all
other RTC power planes are on
I Test Point: This signal must have an external pull-up to VccSus3_3.
2.17 AC ’97 Link
Table 2-17. AC ’97 Link Signals
Name
AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN[1:0]
Type
O
O
I
O
I
Description
AC ’97 Reset: Master H/W reset to external Codec(s)
AC ’97 Sync: 48 kHz fixed rate sample sync to the Codec(s)
AC ’97 Bit Clock: 12.288 MHz serial data clock generated by the external
Codec(s). This signal has an integrated pull-down resistor.
AC ’97 Serial Data Out: Serial TDM data output to the Codec(s)
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a functional
strap. See Section 2.20.1 for more details.
AC ’97 Serial Data In 0: Serial TDM data inputs from the Codecs.
Intel^® 82801CA ICH3-S Datasheet
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