82801CA Datasheet, PDF (307/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.3.2
9.3.3
SBYTE_FMT—Interval Timer Status Byte Format Register
I/O Address:
Default Value:
Counter 0 = 40h,
Counter 1 = 41h,
Counter 2 = 42h
Bits[6:0] undefined, Bit 7=0
Attribute:
Size:
RO
8 bits per counter
Each counter's status byte can be read following a Read Back Command. If latch status is chosen
(bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the
counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter
2) returns the status byte. The status byte returns the following:
Bit
Description
Counter OUT Pin State—RO.
7 _{0 = OUT pin of the counter is also a 0.}
1 = OUT pin of the counter is also a 1.
Count Register Status—RO. This bit indicates when the last count written to the Count Register
(CR) has been loaded into the counting element (CE). The exact time this happens depends on the
counter mode, but until the count is loaded into the counting element (CE), the count value will be
6 _incorrect.
0 = Count has been transferred from CR to CE and is available for reading.
1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading.
Read/Write Selection Status—RO. These reflect the read/write selection made through bits[5:4] of
the control register. The binary codes returned during the status read match the codes used to
program the counter read/write selection.
5:4 ^{00 = Counter Latch Command}
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Mode Selection Status—RO. These bits return the counter mode programming. The binary code
returned matches the code used to program the counter mode, as listed under the bit function above.
000 = Mode 0Out signal on end of count (=0)
001 = Mode 1Hardware retriggerable one-shot
3:1 _{x10 = Mode 2Rate generator (divide by n counter)}
x11 = Mode 3Square wave output
100 = Mode 4Software triggered strobe
101 = Mode 5Hardware triggered strobe
Countdown Type Status—RO. This bit reflects the current countdown type.
0 _{0 = Binary countdown.}
1 = Binary Coded Decimal (BCD) countdown.
Counter Access Ports Register
I/O Address:
Default Value:
Counter 0–40h,
Counter 1–41h,
Counter 2–42h
All bits undefined
Attribute:
R/W
Size:
8 bit
Bit
Description
Counter Port—R/W. Each counter port address is used to program the 16-bit Count Register. The
7:0
order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval
Counter Control Register at port 43h. The counter port is also used to read the current count from the
Count Register, and return the status of the counter programming following a Read Back Command.
Intel^® 82801CA ICH3-S Datasheet
307